SWRS212B May   2017  – April 2018 IWR1642

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
      1. Table 4-3 PAD IO Register Bit Descriptions
    3. 4.3 Signal Descriptions
      1. Table 4-4 Signal Descriptions - Digital
      2. Table 4-5 Signal Descriptions - Analog
    4. 4.4 Pin Multiplexing
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Supply Specifications
    6. 5.6  Power Consumption Summary
    7. 5.7  RF Specification
    8. 5.8  CPU Specifications
    9. 5.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 5.10 Timing and Switching Characteristics
      1. 5.10.1  Power Supply Sequencing and Reset Timing
      2. 5.10.2  Input Clocks and Oscillators
        1. 5.10.2.1 Clock Specifications
      3. 5.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.10.3.1 Peripheral Description
        2. 5.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-7   SPI Timing Conditions
          2. Table 5-8   SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-9   SPI Master Mode Input Timing Requirements (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          4. Table 5-10 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          5. Table 5-11 SPI Master Mode Input Requirements (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.10.3.3 SPI Slave Mode I/O Timings
          1. Table 5-12 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          2. Table 5-13 SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 5.10.4  LVDS Interface Configuration
        1. 5.10.4.1 LVDS Interface Timings
      5. 5.10.5  General-Purpose Input/Output
        1. Table 5-15 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 5.10.6  Controller Area Network Interface (DCAN)
        1. Table 5-16 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 5.10.7  Serial Communication Interface (SCI)
        1. Table 5-17 SCI Timing Requirements
      8. 5.10.8  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-18 I2C Timing Requirements
      9. 5.10.9  Quad Serial Peripheral Interface (QSPI)
        1. Table 5-19 QSPI Timing Conditions
        2. Table 5-20 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-21 QSPI Switching Characteristics
      10. 5.10.10 ETM Trace Interface
        1. Table 5-22 ETMTRACE Timing Conditions
        2. Table 5-23 ETM TRACE Switching Characteristics
      11. 5.10.11 Data Modification Module (DMM)
        1. Table 5-24 DMM Timing Requirements
      12. 5.10.12 JTAG Interface
        1. Table 5-25 JTAG Timing Conditions
        2. Table 5-26 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-27 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Processor Subsystem
      3. 6.3.3 Host Interface
      4. 6.3.4 Master Subsystem Cortex-R4F Memory Map
      5. 6.3.5 DSP Subsystem Memory Map
    4. 6.4 Other Subsystems
      1. 6.4.1 ADC Channels (Service) for User Application
        1. Table 6-3 GP-ADC Parameter
  7. 7 Monitoring and Diagnostics
    1. 7.1 Monitoring and Diagnostic Mechanisms
      1. 7.1.1 Error Signaling Module
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Reference Schematic
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
      3. 8.3.3 Stackup Details
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Community Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Export Control Notice
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information
      1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.4 Pin Multiplexing

Table 4-6 Pin Multiplexing

ADDRESS BALL NUMBER MUXMODE[15:During Power Up] SETTINGS
During Power Up 0 1 2 4 5 6 7 8 9 10 11 12 13 14 15
0xFFFFEA00 P13 GPIO_12 SPI_HOST_INTR SPIB_cs_n_1
0xFFFFEA04 H13 GPIO_13 GPIO_0 PMIC_CLKOUT ePWM1b ePWM2a
0xFFFFEA08 J13 GPIO_16 GPIO_1 SYNC_OUT DMM_MUX_IN SPIB_cs_n_1 SPIB_cs_n_2 ePWM1SYNCI
0xFFFFEA0C D13 GPIO_19 SPIA_mosi Reserved DSS_uart_tx
0xFFFFEA10 E14 GPIO_20 SPIA_miso Reserved
0xFFFFEA14 E13 GPIO_3 SPIA_clk CAN_rx DSS_uart_tx
0xFFFFEA18 C13 GPIO_30 SPIA_cs_n CAN_tx
0xFFFFEA1C F13 GPIO_21 SPIB_mosi I2C_sda
0xFFFFEA20 G14 GPIO_22 SPIB_miso I2C_scl DSS_uart_tx
0xFFFFEA24 F14 GPIO_5 SPIB_clk MSS_uarta_rx MSS_uartb_tx BSS_uart_tx Reserved
0xFFFFEA28 H14 GPIO_4 SPIB_cs_n MSS_uarta_tx MSS_uartb_tx BSS_uart_tx QSPI_clk_ext Reserved
0xFFFFEA2C R13 GPIO_8 QSPI[0] SPIB_miso
0xFFFFEA30 N12 GPIO_9 QSPI[1] SPIB_mosi SPIB_cs_n_2
0xFFFFEA34 R14 GPIO_10 QSPI[2] Reserved
0xFFFFEA38 P12 GPIO_11 QSPI[3] Reserved
0xFFFFEA3C R12 GPIO_7 QSPI_clk SPIB_clk DSS_uart_tx
0xFFFFEA40 P11 GPIO_6 QSPI_cs_n SPIB_cs_n
0xFFFFEA44 N7 nERROR_IN
0xFFFFEA48 N9 Warm_Reset
0xFFFFEA4C N6 nERROR_OUT
0xFFFFEA50 P10 GPIO_17 TCK MSS_uartb_tx Reserved
0xFFFFEA54 N10 GPIO_18 TMS BSS_uart_tx Reserved
0xFFFFEA58 R11 GPIO_23 TDI MSS_uarta_rx
0xFFFFEA5C N13 SOP[0] GPIO_24 TDO MSS_uarta_tx MSS_uartb_tx BSS_uart_tx NDMM_EN
0xFFFFEA60 N8 GPIO_25 MCU_CLKOUT ePWM1a
0xFFFFEA64 K13 GPIO_26 GPIO_2 OSC_CLKOUT MSS_uartb_tx BSS_uart_tx SYNC_OUT PMIC_CLKOUT
0xFFFFEA68 P9 SOP[2] GPIO_27 PMIC_CLKOUT ePWM1b ePWM2a
0xFFFFEA6C P4 GPIO_28 SYNC_IN MSS_uartb_rx DMM_MUX_IN SYNC_OUT
0xFFFFEA70 G13 SOP[1] GPIO_29 SYNC_OUT DMM_MUX_IN SPIB_cs_n_1 SPIB_cs_n_2
0xFFFFEA74 N4 GPIO_15 rs232_rx MSS_uarta_rx BSS_uart_tx MSS_uartb_rx Reserved I2C_scl ePWM2a ePWM2b ePWM3a
0xFFFFEA78 N5 GPIO_14 rs232_tx MSS_uarta_tx MSS_uartb_tx BSS_uart_tx Reserved I2C_sda ePWM1a ePWM1b NDMM_EN ePWM2a
0xFFFFEA7C R4 TRACE_DATA_0 GPIO_31 DMM0 MSS_uarta_tx
0xFFFFEA80 P5 TRACE_DATA_1 GPIO_32 DMM1
0xFFFFEA84 R5 TRACE_DATA_2 GPIO_33 DMM2
0xFFFFEA88 P6 TRACE_DATA_3 GPIO_34 DMM3 ePWM3SYNCO
0xFFFFEA8C R7 TRACE_DATA_4 GPIO_35 DMM4 ePWM2SYNCO
0xFFFFEA90 P7 TRACE_DATA_5 GPIO_36 DMM5 MSS_uartb_tx
0xFFFFEA94 R8 TRACE_DATA_6 GPIO_37 DMM6 BSS_uart_tx
0xFFFFEA98 P8 TRACE_DATA_7 GPIO_38 DMM7 DSS_uart_tx
0xFFFFEA9C D14 TRACE_DATA_8 GPIO_39 DMM8 Reserved ePWM1SYNCI
0xFFFFEAA0 B14 TRACE_DATA_9 GPIO_40 DMM9 Reserved ePWM1SYNCO
0xFFFFEAA4 B15 TRACE_DATA_10 GPIO_41 DMM10 ePWM3a
0xFFFFEAA8 C9 TRACE_DATA_11 GPIO_42 DMM11 ePWM3b
0xFFFFEAAC C8 TRACE_DATA_12 GPIO_43 DMM12 ePWM1a CAN_tx
0xFFFFEAB0 B9 TRACE_DATA_13 GPIO_44 DMM13 ePWM1b CAN_rx
0xFFFFEAB4 B8 TRACE_DATA_14 GPIO_45 DMM14 ePWM2a
0xFFFFEAB8 A9 TRACE_DATA_15 GPIO_46 DMM15 ePWM2b
0xFFFFEABC N15 TRACE_CLK GPIO_47 DMM_CLK
0xFFFFEAC0 N14 TRACE_CTL RESERVED DMM_SYNC