|tsu(D-SCLK)||Setup time, d[3:0] valid before falling sclk edge||7.3||ns|
|th(SCLK-D)||Hold time, d[3:0] valid after falling sclk edge||1.5||ns|
|tsu(D-SCLK)||Setup time, final d[3:0] bit valid before final falling sclk edge||7.3 – P(3)||ns|
|th(SCLK-D)||Hold time, final d[3:0] bit valid after final falling sclk edge||1.5 + P(3)||ns|
(1) Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation.
(2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that launch data on the falling edge in Clock Mode 0.
(3) P = SCLK period in ns.