SWRS219E October   2018  – June 2021 IWR6443 , IWR6843

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions - Digital
      2. 7.2.2 Signal Descriptions - Analog
    3. 7.3 Pin Attributes
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
    6. 8.6  Power Consumption Summary
    7. 8.7  RF Specification
    8. 8.8  CPU Specifications
    9. 8.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1  Power Supply Sequencing and Reset Timing
      2. 8.10.2  Input Clocks and Oscillators
        1. 8.10.2.1 Clock Specifications
      3. 8.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.10.3.1 Peripheral Description
        2. 8.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 8.10.3.2.1 SPI Timing Conditions
          2. 8.10.3.2.2 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
          3. 8.10.3.2.3 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
        3. 8.10.3.3 SPI Slave Mode I/O Timings
          1. 8.10.3.3.1 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 8.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 8.10.4  LVDS Interface Configuration
        1. 8.10.4.1 LVDS Interface Timings
      5. 8.10.5  General-Purpose Input/Output
        1. 8.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) (1) (1)
      6. 8.10.6  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 8.10.6.1 Dynamic Characteristics for the CANx TX and RX Pins
      7. 8.10.7  Serial Communication Interface (SCI)
        1. 8.10.7.1 SCI Timing Requirements
      8. 8.10.8  Inter-Integrated Circuit Interface (I2C)
        1. 8.10.8.1 I2C Timing Requirements (1)
      9. 8.10.9  Quad Serial Peripheral Interface (QSPI)
        1. 8.10.9.1 QSPI Timing Conditions
        2. 8.10.9.2 Timing Requirements for QSPI Input (Read) Timings (1) (1)
        3. 8.10.9.3 QSPI Switching Characteristics
      10. 8.10.10 ETM Trace Interface
        1. 8.10.10.1 ETMTRACE Timing Conditions
        2. 8.10.10.2 ETM TRACE Switching Characteristics
      11. 8.10.11 Data Modification Module (DMM)
        1. 8.10.11.1 DMM Timing Requirements
      12. 8.10.12 JTAG Interface
        1. 8.10.12.1 JTAG Timing Conditions
        2. 8.10.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.10.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Processor Subsystem
      3. 9.3.3 Host Interface
      4. 9.3.4 Main Subsystem Cortex-R4F
      5. 9.3.5 DSP Subsystem
      6. 9.3.6 Hardware Accelerator
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Channels (Service) for User Application
        1. 9.4.1.1 GP-ADC Parameter
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
      1. 10.1.1 Error Signaling Module
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for ABL, 10.4 × 10.4 mm

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
  • ALA|209
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Revision History

Changes from October 1, 2020 to June 30, 2021 (from Revision D (Oct 2020) to Revision E (June 2021))

  • Global: Added/Updated Functional Safety-Compliant targeted informationGo
  • Global: Updated to reflect Functional Safety-ComplianceGo
  • Global: Updated/Changed Master Subsystem to Main Subsystem and Master R4F to MSS R4FGo
  • Global: Updated/Changed A2D to ADCGo
  • (Features) : Updated Functional-Safety Compliance Certification CollateralGo
  • (Device Information) : Added additional Secure production parts for IWR6843Go
  • Updated/Changed Functional Block Diagram Go
  • (Device Comparison):Updated/Changed SIL row to reflect Functional Safety-Compliance for IWR6843Go
  • (Device Comparison): Added a table-note about LVDS and Non-Functional Safety Variant InformationGo
  • (Device Comparison): Updated/Changed the IWR6843AOP Product status from "AI" to "PD" Go
  • (Pin Attributes): Updated/Changed table to remove unsupported mux modes and deleted unsupported CAN signal names.Go
  • (Absolute Maximum Ratings): Added entries for externally supplied power on the RF inputs (TX and RX) and a table-note for the signal level applied on TX.Go
  • (ESD Ratings): Changed HBM ESD value from ±1000 V to ±2000 V, CDM ESD value from ±250 V to ±500 V and added footnote about corner pins.Go
  • Peripheral Description: Added "The SPI uses a MibSPI Protocol by TI" to MibSPI peripheral descriptionGo
  • Transmit Subsystem (Per Channel): Updated/Changed figure.Go
  • Updated/changed "Master" to "Main" in Processor Subsystem imageGo
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect Functional Safety-ComplianceGo
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed Master R4F to MSS R4F and Master SS to Main SSGo
  • (Device Nomenclature):Updated/changed figure to reflect Functional Safety-Compliance, SIL 2 for Safety Level BGo
  • (Tray Information for ABL, 10.4 × 10.4 mm): Added tray information for secure parts.Go