SNOSDI7 December   2023 LDC5071-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Diagnostics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Supply Voltage
      2. 6.3.2 Excitation Signal
      3. 6.3.3 Signal Processing Block
        1. 6.3.3.1 Demodulation
        2. 6.3.3.2 Fixed Gain Control
        3. 6.3.3.3 Automatic Gain Control
      4. 6.3.4 Output Stage
      5. 6.3.5 Diagnostics
        1. 6.3.5.1 Undervoltage Diagnostics
        2. 6.3.5.2 Initialization Diagnostics
        3. 6.3.5.3 Normal State Diagnostics
        4. 6.3.5.4 Fault State Diagnostics
    4. 6.4 Device Functional Modes
      1. 6.4.1 IDLE State
      2. 6.4.2 DIAGNOSTICS State
      3. 6.4.3 NORMAL State
      4. 6.4.4 FAULT State
      5. 6.4.5 DISABLED State
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 5-V Supply Mode
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 VREG and VCC
          2. 7.2.1.2.2 Output Capacitors
          3. 7.2.1.2.3 Automatic Gain Control (AGC) Mode
        3. 7.2.1.3 Application Curve
      2. 7.2.2 3.3-V Supply Mode
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 VREG and VCC
          2. 7.2.2.2.2 Output Capacitors
          3. 7.2.2.2.3 Fixed Gain Mode
      3. 7.2.3 Redundancy Mode
      4. 7.2.4 Single-Ended Mode
      5. 7.2.5 External Diagnostics Required for Loss of VCC or GND
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Mode 1: VCC = 5 V, VREG = 3.3 V
      2. 7.3.2 Mode 2: VCC = VREG = 3.3 V
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

The designer requires at least a 2-layer PCB for the LDC5071-Q1. The device is designed such that one half of the device contains sensitive analog signals for the sensor coils (LCIN, LCOUT, and INxx), and the other half of the device contains signals that may leave the PCB (power, ground, and analog outputs).

The following lists the best practices for the PCB layout:

  • Please the bypass capacitors close to the device pins.
  • Place a ground plane layer below the LDC5071-Q1.
  • Ideally, there should not be a ground layer beneath the sensor coils as it will impact the sensor response. A shielding layer, however, may be implemented to protect the sensor from interference of metal or EMI beneath the sensor. To minimize the impact to the sensor response, separate the shielding layer by as much distance from the bottom of the sensor as possible.
  • Keep the LCIN, LCOUT, and the INX signal traces as short as possible between the LDC5071-Q1 device and the sensor coils.
  • Accommodate placeholder pads in the layout for the RINFLT, CFLT, L1, L2, L3, and L4. These pads can be useful in debug during EMI/EMC testing and can save iteration of board layout.