SNVS446D June   2006  – January 2016 LM1771

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Timing Opinion
      2. 7.3.2 Short-Circuit Protection
      3. 7.3.3 Precision Enable
      4. 7.3.4 Soft-Start
      5. 7.3.5 Jitter
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 LM1771 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Design Guide
            1. 8.2.1.2.1.1 Frequency Selection
            2. 8.2.1.2.1.2 Inductor Selection
            3. 8.2.1.2.1.3 Output Capacitor
            4. 8.2.1.2.1.4 Feedforward Capacitor
            5. 8.2.1.2.1.5 Input Capacitor
          2. 8.2.1.2.2 MOSFET Selection
            1. 8.2.1.2.2.1 VDS Voltage Rating
            2. 8.2.1.2.2.2 RDSON
            3. 8.2.1.2.2.3 Gate Drive
            4. 8.2.1.2.2.4 Gate Charge
            5. 8.2.1.2.2.5 Rise and Fall Times
            6. 8.2.1.2.2.6 Gate Charge Ratio
            7. 8.2.1.2.2.7 Feedback Resistors
          3. 8.2.1.2.3 Efficiency Calculations
            1. 8.2.1.2.3.1 Quiescent Current
            2. 8.2.1.2.3.2 Conduction Loss
            3. 8.2.1.2.3.3 Switching Loss
            4. 8.2.1.2.3.4 Transitional Loss
            5. 8.2.1.2.3.5 DCR Loss
            6. 8.2.1.2.3.6 Efficiency
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Example Application 5 VIN to 1.8 VOUT
      3. 8.2.3 Example Application 5 VIN to 3.3 VOUT
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The LM1771, like all switching regulators, requires careful attention to layout to ensure optimal performance. The following steps must be taken to aid in the layout. For more information refer to Application Note AN-1299 (SNVA074).

  1. Ensure that the ground connections of the input capacitor, output capacitor and NMOS are as close as possible. Ideally these must all be grounded together in close proximity on the component side of the board.
  2. Keep the switch node small to minimize EMI without degrading thermal cooling of the FETs.
  3. Locate the feedback resistors close to the IC and keep the feedback trace as short as possible. Do not run any feedback traces near the switch node.
  4. Keep the gate traces short and keep them away from the switch node as much as possible.
  5. If a small bypass capacitor is used on VIN (0.1 µF) place it as close to the pin, with the ground connection as close to the chip ground, as possible.

10.2 Layout Examples

LM1771 layout_new_SNVS446_2.gif Figure 26. LM1771 Layout Example (Top)
LM1771 typical_layout_BOTTOM_LM1771_snvs446.png Figure 27. LM1771 Layout Example (Bottom)

10.3 Thermal Considerations

By breaking down the individual power loss in each component it makes it easy to determine the temperature rise of each component. Generally the expected temperature rise of the LM1771 is extremely low as it is not in the power path. Therefore the only two items of concern are the PMOS and the NMOS. The power loss in the PMOS is the sum of the conduction loss and transitional loss, while the NMOS only has conduction loss. It is assumed that any loss associated with the body diode conduction during the dead-time is negligible.

For completeness of design it is important to watch out for the temperature rise of the inductor. Assuming the inductor is kept out of saturation the predominant loss is the DC copper resistance. At higher frequencies, depending on the core material, the core loss could approach or exceed the DCR losses. Consult with the inductor manufacturer for appropriate temp curves based on current.