SNVSC03A June   2021  – February 2023 LM25148-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings 
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN)
      2. 8.3.2  High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
      3. 8.3.3  Precision Enable (EN)
      4. 8.3.4  Power-Good Monitor (PG)
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Dual Random Spread Spectrum (DRSS)
      7. 8.3.7  Soft Start
      8. 8.3.8  Output Voltage Setpoint (FB)
      9. 8.3.9  Minimum Controllable On Time
      10. 8.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      11. 8.3.11 Slope Compensation
      12. 8.3.12 Inductor Current Sense (ISNS+, VOUT)
        1. 8.3.12.1 Shunt Current Sensing
        2. 8.3.12.2 Inductor DCR Current Sensing
      13. 8.3.13 Hiccup Mode Current Limiting
      14. 8.3.14 High-Side and Low-Side Gate Drivers (HO, LO)
      15. 8.3.15 Output Configurations (CNFG)
      16. 8.3.16 Single-Output Dual-Phase Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
      3. 8.4.3 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 Power MOSFETs
        5. 9.1.1.5 EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High Efficiency 2.1-MHz Synchronous Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design with WEBENCH® Tools
          2. 9.2.1.2.2 Buck Inductor
          3. 9.2.1.2.3 Current-Sense Resistance
          4. 9.2.1.2.4 Output Capacitors
          5. 9.2.1.2.5 Input Capacitors
          6. 9.2.1.2.6 Frequency Set Resistor
          7. 9.2.1.2.7 Feedback Resistors
          8. 9.2.1.2.8 Compensation Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – High Efficiency 440-kHz Synchronous Buck Regulator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Design 3 – Dual-Phase 400-kHz 20-A Synchronous Buck Regulator
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate-Drive Layout
        3. 9.4.1.3 PWM Controller Layout
        4. 9.4.1.4 Thermal Design and Layout
        5. 9.4.1.5 Ground Plane Design
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design with WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Connect the exposed pad to AGND and PGND on the PCB.
Figure 6-1 24-Pin VQFN RGY Package with Wettable Flanks(Top View)
Table 6-1 Pin Functions
PIN I/O(1) DESCRIPTION
NO. NAME
1 NC ­­̶̶ Connect to GND at the exposed pad to improve heat spreading.
2 NC ­­̶̶ Connect to GND at the exposed pad to improve heat spreading.
3 CNFG I Connect a resistor to ground to set primary/secondary, spread spectrum enable/disable, or interleaved operation.
4 RT I Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100 kHz and 2.2 MHz.
5 EXTCOMP O Transconductance error amplifier output. If used, connect the compensation network from EXTCOMP to AGND.
6 FB I Connect FB to VDDA to set the output voltage to 3.3 V. Connect FB using a 24.9 kΩ or 49.9 kΩ to VDDA to set the output voltage to 5 V or 12 V, respectively. Install a resistor divider from VOUT to AGND to set the output voltage setpoint between 0.8 V and 36 V. The FB regulation voltage is 0.8 V.
7 AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits
8 VDDA O Internal analog bias regulator. Connect a ceramic decoupling capacitor from VDDA to AGND.
9 VCC P VCC bias supply pin. Connect a ceramic capacitor between VCC and PGND.
10 PGND G Power ground connection pin for low-side MOSFET gate driver
11 LO O Low-side power MOSFET gate driver output
12 VIN P Supply voltage input source for the VCC regulator
13 HO O High-side power MOSFET gate driver output
14 SW P Switching node of the buck regulator and high-side gate driver return. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
15 CBOOT P High-side driver supply for bootstrap gate drive
16 VCCX P Optional input for an external bias supply. If VVCCX > 4.3 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled.
17 PG/SYNCOUT O An open-collector output that goes low if VOUT is outside the specified regulation window. The PG/SYNCOUT pin of the primary controller in dual-phase mode provides a 180° phase-shifted SYNCOUT signal.
18 PFM/SYNC I Connect PFM/SYNC to VDDA to enable diode emulation mode. Connect PFM to AGND to operate the LM25148-Q1 in forced PWM (FPWM) mode with continuous conduction at light loads. PFM can also be used as a synchronization input to synchronize the internal oscillator to an external clock signal.
19 EN I An active-high precision input with rising threshold of 1 V and hysteresis current of 10 µA. If the EN voltage is less than 0.5 V, the LM25148-Q1 is in shutdown mode, unless a SYNC signal is present on PFM/SYNC.
20 ISNS+ I Current sense amplifier input. Connect this pin to the inductor side of the external current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low-current Kelvin connection.
21 VOUT I Output voltage sense and the current sense amplifier input. Connect VOUT to the output side of the current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used).
22 NC — Connect to GND at the exposed pad to improve heat spreading.
23 NC — Connect to GND at the exposed pad to improve heat spreading.
24 NC ­­— Connect to GND at the exposed pad to improve heat spreading.
(1) P = Power, G = Ground, I = Input, O = Output