SNVS479I January   2007  – April 2026 LM25575

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Shutdown and Stand-by Mode
      2. 6.3.2 Soft Start
      3. 6.3.3 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 High Voltage Start-Up Regulator
      2. 6.4.2 Oscillator and Sync Capability
      3. 6.4.3 Error Amplifier and PWM Comparator
      4. 6.4.4 Ramp Generator
      5. 6.4.5 Maximum Duty Cycle and Input Drop-out Voltage
      6. 6.4.6 Boost Pin
      7. 6.4.7 Current Limit
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 BIas Power Dissipation Reduction
    2. 7.2 Typical Application
      1. 7.2.1 Typical Schematic for High Frequency (1MHz) Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Custom Design With WEBENCH® Tools
        2. 7.2.3.2  R3 (RT)
        3. 7.2.3.3  L1
        4. 7.2.3.4  C3 (CRAMP)
        5. 7.2.3.5  C9, C10
        6. 7.2.3.6  D1
        7. 7.2.3.7  C1, C2
        8. 7.2.3.8  C8
        9. 7.2.3.9  C7
        10. 7.2.3.10 C4
        11. 7.2.3.11 R5, R6
        12. 7.2.3.12 R1, R2, C12
        13. 7.2.3.13 R7, C11
        14. 7.2.3.14 R4, C5, C6
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Layout and Thermal Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Developmental Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

LM25575 PWP 16-Lead HTSSOP (Top View)Figure 4-1 PWP 16-Lead HTSSOP (Top View)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NO. NAME
1VCCOOutput of the bias regulator
Vcc tracks Vin up to 9V. Beyond 9V, Vcc is regulated to 7 Volts. A 0.1 uF to 1uF ceramic decoupling capacitor is required. An external voltage (7.5V – 14V) can be applied to this pin to reduce internal power dissipation.
2SD I Shutdown or UVLO input
If the SD pin voltage is below 0.7V the regulator will be in a low power state. If the SD pin voltage is between 0.7V and 1.225V the regulator will be in standby mode. If the SD pin voltage is above 1.225V the regulator will be operational. An external voltage divider can be used to set a line undervoltage shutdown threshold. If the SD pin is left open circuit, a 5 µA pull-up current source configures the regulator fully operational.
3VIN I Input supply voltage
Nominal operating range: 6V to 42V
4SYNC I Oscillator synchronization input or output
The internal oscillator can be synchronized to an external clock with an external pull-down device. Multiple LM25575 devices can be synchronized together by connection of the SYNC pins.
5COMP O Output of the internal error amplifier
The loop compensation network must be connected between this pin and the FB pin.
6FB I Feedback signal from the regulated output
This pin is connected to the inverting input of the internal error amplifier. The regulation threshold is 1.225V.
7RT I Internal oscillator frequency set input. The internal oscillator is set with a single resistor, connected between this pin and the AGND pin.
8RAMP O Ramp control signal
An external capacitor connected between this pin and the AGND pin sets the ramp slope used for current mode control. Recommended capacitor range 50 pF to 2000pF.
9AGND GND Analog ground
Internal reference for the regulator control functions
10SS O Soft-start
An external capacitor and an internal 10 µA current source set the time constant for the rise of the error amp reference. The SS pin is held low during standby, Vcc UVLO and thermal shutdown.
11OUT O Output voltage connection
Connect directly to the regulated output voltage.
12PGND GND Power ground
Low side reference for the PRE switch and the IS sense resistor.
13IS I Current sense
Current measurement connection for the re-circulating diode. An internal sense resistor and a sample/hold circuit sense the diode current near the conclusion of the off-time. This current measurement provides the DC level of the emulated current ramp.
14SW O Switching node
The source terminal of the internal buck switch. The SW pin must be connected to the external Schottky diode and to the buck inductor.
15PRE O Pre-charge assist for the bootstrap capacitor
This open drain output can be connected to SW pin to aid charging the bootstrap capacitor during very light load conditions or in applications where the output can be pre-charged before the LM25575 is enabled. An internal pre-charge MOSFET is turned on for 250 ns each cycle just prior to the on-time interval of the buck switch.
16BST I Boost input for bootstrap capacitor
An external capacitor is required between the BST and the SW pins. A 0.022 µF ceramic capacitor is recommended. The capacitor is charged from Vcc through an internal diode during the off-time of the buck switch.
NAEP _ Exposed Pad
Exposed metal pad on the underside of the device. It is recommended to connect this pad to the PWB ground plane, to aid in heat dissipation.
(1) I = input, O = output