SNVS576F August   2008  – February 2015 LM26003 , LM26003-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application Circuit
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings: LM26003
    3. 7.3 ESD Ratings: LM26003-Q1
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 FPWM
      2. 8.3.2 Soft-Start
      3. 8.3.3 Current Limit
      4. 8.3.4 Frequency Adjustment and Synchronization
      5. 8.3.5 VBIAS
      6. 8.3.6 Low VIN Operation and UVLO
      7. 8.3.7 PGOOD
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable
      2. 8.4.2 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting Output Voltage
        2. 9.2.2.2 Inductor
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 Input Capacitor
        5. 9.2.2.5 Bootstrap
        6. 9.2.2.6 Catch Diode
        7. 9.2.2.7 Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations and TSD
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

20-Pin
TSSOP Package
Top View
LM26003 LM26003-Q1 30067602.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VIN 1 I Power supply input for high side FET
VIN 2 I Power supply input for high side FET
VIN 3 I Power supply input for high side FET
AVIN 4 I Power supply input for IC supply
PGOOD 5 O Power Good pin. An open-drain output which goes high when the output voltage is greater than 92% of nominal.
EN 6 I Enable is an analog level input pin. When pulled below 0.8 V, the device enters shutdown mode.
SS 7 I Soft-start pin. Connect a capacitor from this pin to GND to set the soft-start time.
COMP 8 I Compensation pin. Connect to a resistor capacitor pair to compensate the control loop.
FB 9 I Feedback pin. Connect to a resistor divider between VOUT and GND to set output voltage.
AGND 10 GND Analog GND as IC reference
PGND 11 GND Power GND is GND for the switching stage of the regulator
FREQ 12 O Frequency adjust pin. Connect a resistor from this pin to GND to set the operating frequency.
FPWM 13 I FPWM is a logic level input pin. For normal operation, connect to GND. When pulled high, sleep mode operation is disabled.
SYNC 14 I Frequency synchronization pin. Connect to an external clock signal for synchronized operation. SYNC must be pulled low for non-synchronized operation.
VBIAS 15 I Connect to an external 3-V or greater supply to bypass the internal regulator for improved efficiency. If not used, VBIAS should be tied to GND.
VDD 16 O The output of the internal regulator. Bypass with a minimum 1.0-µF capacitor.
BOOT 17 I Bootstrap capacitor pin. Connect a 0.1-µF minimum ceramic capacitor from this pin to SW to generate the gate drive bootstrap voltage.
SW 18 O Switch pin. The source of the internal N-channel switch.
SW 19 O Switch pin. The source of the internal N-channel switch.
SW 20 O Switch pin. The source of the internal N-channel switch.
EP EP GND Exposed Pad thermal connection. Connect to GND.