SNVS576F August   2008  – February 2015 LM26003 , LM26003-Q1


  1. Features
  2. Applications
  3. Description
  4. Typical Application Circuit
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings: LM26003
    3. 7.3 ESD Ratings: LM26003-Q1
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 FPWM
      2. 8.3.2 Soft-Start
      3. 8.3.3 Current Limit
      4. 8.3.4 Frequency Adjustment and Synchronization
      5. 8.3.5 VBIAS
      6. 8.3.6 Low VIN Operation and UVLO
      7. 8.3.7 PGOOD
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable
      2. 8.4.2 Sleep Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Setting Output Voltage
        2. Inductor
        3. Output Capacitor
        4. Input Capacitor
        5. Bootstrap
        6. Catch Diode
        7. Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations and TSD
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Good board layout is critical for switching regulators such as the LM26003 device. First, the ground plane area must be sufficient for thermal dissipation purposes, and second, appropriate guidelines must be followed to reduce the effects of switching noise.

Switch mode converters are very fast switching devices. In such devices, the rapid increase of input current combined with parasitic trace inductance generates unwanted Ldi/dt noise spikes at the SW node and also at the VIN node. The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may turn into electromagnetic interference (EMI) and can also cause problems in device performance. Therefore, care must be taken in layout to minimize the effect of this switching noise.

The current sensing circuit in current mode devices can be easily affected by switching noise. This noise can cause duty-cycle jitter which leads to increased spectrum noise. Although the LM26003 device has 150 ns blanking time at the beginning of every cycle to ignore this noise, some noise may remain after the blanking time. Following the important guidelines below will help minimize switching noise and its effect on current sensing.

The switch node area should be as small as possible. The catch diode, input capacitors, and output capacitors should be grounded to the same local ground, with the bulk input capacitor grounded as close as possible to the catch diode anode. Additionally, the ground area between the catch diode and bulk input capacitor is very noisy and should be somewhat isolated from the rest of the ground plane.

A ceramic input capacitor must be connected as close as possible to the AVIN pin as well as PVIN pin. The capacitor between AVIN and ground should be grounded close to the GND pins of the LM26003 device and the PVIN capacitor should be grounded close to the Schottky diode ground. Often, the AVIN bypass capacitor is most easily located on the bottom side of the PCB. It increases trace inductance due to the vias, it reduces trace length however.

The above layout recommendations are illustrated in Figure 22.

It is a good practice to connect the EP, GND pin, and small signal components (COMP, FB, FREQ) to a separate ground plane, shown in Figure 22 as EP GND, and in the schematics as a signal ground symbol. Both the exposed pad and the GND pin must be connected to ground. This quieter plane should be connected to the high current ground plane at a quiet location, preferably near the Vout ground as shown by the dashed line in Figure 22.

The EP GND plane should be made as large as possible, since it is also used for thermal dissipation. Several vias can be placed directly below the EP to increase heat flow to other layers when they are available. The recommended via hole diameter is 0.3mm.

The trace from the FB pin to the resistor divider should be short and the entire feedback trace must be kept away from the inductor and switch node. See AN-1229 SIMPLE SWITCHER ® PCB Layout Guidelines, SNVA054, for more information regarding PCB layout for switching regulators.

11.2 Layout Example

LM26003 LM26003-Q1 30067632.gifFigure 22. Example PCB Layout

11.3 Thermal Considerations and TSD

Although the LM26003 device has a built in current limit, at ambient temperatures above 80°C, device temperature rise may limit the actual maximum load current. Therefore, temperature rise must be taken into consideration to determine the maximum allowable load current.

Temperature rise is a function of the power dissipation within the device. The following equations can be used to calculate power dissipation (PD) and temperature rise, where total PD is the sum of FET switching losses, FET DC losses, drive losses, Iq, and VBIAS losses:

Equation 22. PDTOTAL = PswAC + PswDC + PQG + PIq + PVBIAS
Equation 23. LM26003 LM26003-Q1 30067633.gif
Equation 24. PswDC = D x Iload2 x (0.095 + 0.00065 x (Tj - 25))
Equation 25. PQG = Vin x 9.2 x 10-9 x fsw
Equation 26. PIq = Vin x Iq
Equation 27. PVBIAS = Vbias x IVBIAS

Given this total power dissipation, junction temperature can be calculated as follows:

Equation 28. Tj = Ta + (PDTOTAL x θJA)

Where θJA= 32°C/W (typically) when using a multi-layer board with a large copper plane area. θJA varies with board type and metallization area.

To calculate the maximum allowable power dissipation, assume Tj = 125°C. To ensure that junction temperature does not exceed the maximum operating rating of 125°C, power dissipation should be verified at the maximum expected operating frequency, maximum ambient temperature, and minimum and maximum input voltage. The calculated maximum load current is based on continuous operation and may be exceeded during transient conditions.

If the power dissipation remains above the maximum allowable level, device temperature will continue to rise. When the junction temperature exceeds its maximum, the LM26003 device engages Thermal Shut Down (TSD). In TSD, the part remains in a shutdown state until the junction temperature falls to within normal operating limits. At this point, the device restarts in soft-start mode.