SNVS576F August   2008  – February 2015 LM26003 , LM26003-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application Circuit
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings: LM26003
    3. 7.3 ESD Ratings: LM26003-Q1
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 FPWM
      2. 8.3.2 Soft-Start
      3. 8.3.3 Current Limit
      4. 8.3.4 Frequency Adjustment and Synchronization
      5. 8.3.5 VBIAS
      6. 8.3.6 Low VIN Operation and UVLO
      7. 8.3.7 PGOOD
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable
      2. 8.4.2 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting Output Voltage
        2. 9.2.2.2 Inductor
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 Input Capacitor
        5. 9.2.2.5 Bootstrap
        6. 9.2.2.6 Catch Diode
        7. 9.2.2.7 Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations and TSD
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
Voltages from the indicated
pins to GND		 VIN –0.3 40 V
SW –1 40 V
VDD –0.3 7 V
VBIAS –0.3 10 V
FB -0.3 7 V
BOOT VSW-0.3 VSW+7 V
PGOOD –0.3 7 V
FREQ –0.3 7 V
SYNC –0.3 7 V
EN –0.3 40 V
FPWM –0.3 7 V
Power Dissipation 3.1 W
Recommended Lead Temperature Vapor Phase (70s) 215 °C
Infrared (15s) 220 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

7.2 ESD Ratings: LM26003

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
Charged machine model ±200000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 ESD Ratings: LM26003-Q1

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V
Charged device model (CDM), per AEC Q100-011 Corner pins (1, 10, 11, and 20) ±1000
Other pins ±1000
Charged machine model ±200
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.4 Recommended Operating Conditions

MIN NOM MAX UNIT
Operating Junction Temperature −40 125 °C
Supply Voltage 3.0 38 V

7.5 Thermal Information

THERMAL METRIC(1) LM26003, LM26003-Q1 UNIT
PWP
20 PINS
RθJA Junction-to-ambient thermal resistance 25.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 19.6
RθJB Junction-to-board thermal resistance 16.5
ψJT Junction-to-top characterization parameter 0.5
ψJB Junction-to-board characterization parameter 16.3
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.6 Electrical Characteristics

Unless otherwise stated, Vin = 12 V, TJ = 25°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation.
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
SYSTEM
ISD(2) Shutdown Current EN = 0 V 10.8 µA
EN = 0 V, –40°C ≤ TJ ≤ 125°C 20
IqSleep_VB(2) Quiescent Current Sleep mode, VBIAS = 5 V 40 µA
Sleep mode, VBIAS = 5 V, –40°C ≤ TJ ≤ 125°C 70
IqSleep_VDD Quiescent Current Sleep mode, VBIAS = GND 76 µA
Sleep mode, VBIAS = GND, –40°C ≤ TJ ≤ 125°C 125
IqPWM_VB Quiescent Current PWM mode, VBIAS = 5 V
FPWM = 2 V		 0.16 0.23 mA
IqPWM_VDD Quiescent Current PWM mode, VBIAS = GND
FPWM = 2 V		 0.65 0.85 mA
IBIAS_Sleep(2) Bias Current Sleep mode, VBIAS = 5 V 33 µA
Sleep mode, VBIAS = 5 V, –40°C ≤ TJ ≤ 125°C 60
IBIAS_PWM Bias Current PWM mode, VBIAS = 5 V 0.5 0.7 mA
VFB Feedback Voltage 5 V < Vin < 38 V 1.236 V
5 V < Vin < 38 V, –40°C ≤ TJ ≤ 125°C 1.217 1.255
IFB FB Bias Current VFB = 1.20 V ±200 nA
ΔVOUT/ΔVIN Output Voltage Line Regulation 5 V < Vin < 38 V 0.00025 %/V
ΔVOUT/ΔIOUT Output Voltage Load Regulation 0.8 V < VCOMP < 1.15 V 0.08 %/A
VDD VDD Pin Output Voltage 7 V < Vin < 35 V, IVDD= 0 mA to 5 mA 5.99 V
7 V < Vin < 35 V, IVDD= 0 mA to 5 mA, –40°C ≤ TJ ≤ 125°C 5.50 6.50
ISS_Source Soft-start Source Current 2.5 µA
–40°C ≤ TJ ≤ 125°C 1.5 4.6
Vbias_th VBIAS On Voltage Specified at IBIAS = 92.5% of full value 2.64 2.9 3.07 V
PROTECTION
ILIMPK Peak Current Limit 4.7 A
–40°C ≤ TJ ≤ 125°C 3.15 6.05
VFB_SC Short Circuit Frequency Foldback Threshold Measured at FB falling 0.87 V
F_min_sc Min Frequency in Foldback VFB < 0.3 V 45 kHz
VTH_PGOOD Power Good Threshold Measured at FB, PGOOD rising 92%
Measured at FB, PGOOD rising, –40°C ≤ TJ ≤ 125°C 89% 95%
PGOOD Hysteresis 2% 6% 8%
IPGOOD_HI PGOOD Leakage Current PGOOD = 5 V 1.25 nA
RDS_PGOOD PGOOD On Resistance PGOOD sink current = 500 µA 150 Ω
VUVLO Under-voltage Lock-Out Threshold Vin falling , shutdown, VDD = VIN 2.96 V
Vin falling , shutdown, VDD = VIN, –40°C ≤ TJ ≤ 125°C 2.70 3.30
Vin rising, soft-start, VDD = VIN 3.99
Vin rising, soft-start, VDD = VIN, –40°C ≤ TJ ≤ 125°C 3.70 4.30
TSD Thermal Shutdown Threshold 160 °C
θJA Thermal Resistance Power dissipation = 1W, 0 lfpm air flow 32 °C/W
LOGIC
VthEN Enable Threshold Voltage Enable rising 1.18 V
Enable rising, –40°C ≤ TJ ≤ 125°C 0.8 1.4
Enable Hysteresis 180 mV
IEN_Source EN Source Current EN = 0 V 4.85 µA
VTH_FPWM FPWM Threshold 1.24 V
–40°C ≤ TJ ≤ 125°C 0.8 1.6
IFPWM FPWM Leakage Current FPWM = 5 V 3 nA
EA
gm Error Amp Trans-conductance 675 µmho
–40°C ≤ TJ ≤ 125°C 400 1000
ICOMP COMP Source Current VCOMP = 0.9 V 57 µA
COMP Sink Current VCOMP = 0.9 V 57 µA
VCOMP COMP Pin Voltage Range 0.64 1.27 V
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Iq and ISD specify the current into the VIN and AVIN pins. IBIAS is the current into the VBIAS pin when the VBIAS voltage is greater than 3 V. All quiescent current specifications apply to non-switching operation.

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RDS(ON) Switch On Resistance Isw = 2A 0.095 Ω
Isw = 2A, –40°C ≤ TJ ≤ 125°C 0.040 0.200
Isw_off Switch Off State Leakage Current Vin = 38 V, VSW = 0 V 0.002 μA
Vin = 38 V, VSW = 0 V, –40°C ≤ TJ ≤ 125°C 5.0
fsw Switching Frequency RFREQ = 62k, 124k, 240k, –40°C ≤ TJ ≤ 125°C ±10%
VFREQ FREQ Voltage 1.0 V
fSW range Switching Frequency Range –40°C ≤ TJ ≤ 125°C 150 500 kHz
VSYNC Sync Pin Threshold SYNC rising 1.23 V
SYNC rising, –40°C ≤ TJ ≤ 125°C 1.6
SYNC falling 1.10
SYNC falling, –40°C ≤ TJ ≤ 125°C 0.8
Sync Pin Hysteresis 135 mV
ISYNC SYNC Leakage Current 2 nA
FSYNC_UP Upper Frequency Synchronization Range As compared to nominal fSW, –40°C ≤ TJ ≤ 125°C +30%
FSYNC_DN Lower Frequency Synchronization Range As compared to nominal fSW, –40°C ≤ TJ ≤ 125°C –20%
TOFFMIN Minimum Off-time 300 ns
TONMIN Minimum On-time 190 ns
THSLEEP_HYS Sleep Mode Threshold Hysteresis VFB rising, % of THWAKE 101.3%
THWAKE Wake Up Threshold Measured at falling FB, COMP = 0.6 V 1.236 V
IBOOT BOOT Pin Leakage Current BOOT = 6 V, SW = GND 0.001 μA
BOOT = 6 V, SW = GND, –40°C ≤ TJ ≤ 125°C 5.0

7.8 Typical Characteristics

Unless otherwise specified the following conditions apply: Vin = 12 V, TJ = 25°C.
LM26003 LM26003-Q1 30067637.png
Figure 1. Efficiency vs Load Current (300 kHz)
LM26003 LM26003-Q1 30067634.png
Figure 3. VFB vs Temperature
LM26003 LM26003-Q1 30067635.png
Figure 5. IQ and IVBIAS vs Temperature (Sleep Mode)
LM26003 LM26003-Q1 30067645.png
Figure 9. UVLO Threshold vs Temperature (VDD = VIN)
LM26003 LM26003-Q1 30067639.png
Figure 2. Efficiency vs Load Current (500 kHz)
LM26003 LM26003-Q1 30067636.png
Figure 4. VFB vs Vin (IDC = 300 mA)
LM26003 LM26003-Q1 30067638.png
Figure 6. IQ and IVBIAS vs Temperature (PWM Mode)
LM26003 LM26003-Q1 30067641.png
Figure 7. Peak Current Limit vs Temperature
LM26003 LM26003-Q1 30067643.png
Figure 8. Normalized Switching Frequency vs Temperature (300 kHz)