SBOS960 Data sheet

SBOS960C September 2018 – February 2022 LM2902LV , LM2904LV

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

D|8
- MSOI002K
PW|8
- MPDS568
DGK|8
- MPDS028E
DDF|8
- MPDS569D

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.7 Typical Characteristics

at T_A = 25°C, V+ = 2.75 V, V– = –2.75 V, R_L = 10 kΩ connected to V_S / 2, V_CM = V_S / 2, and V_OUT = V_S / 2 (unless otherwise noted)

Figure 6-1 I_B and I_OS vs Common-Mode Voltage

C_L = 10 pF

Figure 6-3 Open-Loop Gain and Phase vs Frequency

C_L = 10 pF

Figure 6-5 Closed-Loop Gain vs Frequency

Figure 6-2 Open-Loop Gain vs Temperature

Figure 6-4 Open-Loop Gain vs Output Voltage

Figure 6-6 Output Voltage vs Output Current (Claw)

V_S = 2.7 V to 5.5 V

Figure 6-8 DC PSRR vs Temperature

V_CM = (V–) – 0.1 V to (V+) – 1.5 V

Figure 6-10 DC CMRR vs Temperature

Figure 6-7 PSRR vs Frequency

Figure 6-9 CMRR vs Frequency

Figure 6-11 0.1-Hz to 10-Hz Integrated Voltage Noise

Figure 6-12 Input Voltage Noise Spectral Density

V_S = 5.5 V	V_CM = 2.5 V	f = 1 kHz
G = 1	BW = 80 kHz

Figure 6-14 THD + N vs Amplitude

Figure 6-16 Quiescent Current vs Temperature

V_S = 5.5 V	V_CM = 2.5 V	G = 1
BW = 80 kHz	V_OUT = 0.5 V_RMS

Figure 6-13 THD + N vs Frequency

Figure 6-15 Quiescent Current vs Supply Voltage

Figure 6-17 Open-Loop Output Impedance vs Frequency

G = 1	V_IN = 100 mVpp

Figure 6-18 Small Signal Overshoot vs Capacitive Load

Figure 6-20 Phase Margin vs Capacitive Load

G = –10	V_IN = 600 mV_PP

Figure 6-22 Overload Recovery

G = –1	V_IN = 100 mVpp

Figure 6-19 Small Signal Overshoot vs Capacitive Load

G = 1	V_IN = 6.5 V_PP

Figure 6-21 No Phase Reversal

G = 1	V_IN = 100 mV_PP	C_L = 10 pF

Figure 6-23 Small-Signal Step Response

G = 1

C_L = 10 pF

V_IN = 4 V_PP

Figure 6-24 Large-Signal Step Response

G = 1

C_L = 100 pF

2-V step

Figure 6-26 Large-Signal Settling Time (Positive)

Figure 6-28 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency

G = 1

C_L = 100 pF

2-V step

Figure 6-25 Large-Signal Settling Time (Negative)

Figure 6-27 Short-Circuit Current vs Temperature

Figure 6-29 Channel Separation