SNVS515I September   2007  – January 2018 LM3102

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Schematic
      2.      Efficiency vs Load Current (VOUT = 3.3 V)
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  COT Control Circuit Overview
      2. 7.3.2  Start-Up Regulator (VCC)
      3. 7.3.3  Regulation Comparator
      4. 7.3.4  Zero Coil Current Detect
      5. 7.3.5  Overvoltage Comparator
      6. 7.3.6  Current Limit
      7. 7.3.7  N-Channel MOSFET and Driver
      8. 7.3.8  Soft-Start
      9. 7.3.9  Thermal Protection
      10. 7.3.10 Thermal Derating
    4. 7.4 Device Functional Modes
      1. 7.4.1 ON-Time Timer, Shutdown
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Design Steps for the LM3102 Application
        2. 8.2.2.2 External Components
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YPA|28
  • PWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

The LM3102 regulation, overvoltage, and current limit comparators are very fast so they will respond to short duration noise pulses. Layout is therefore critical for optimum performance. It must be as neat and compact as possible, and all external components must be as close to their associated pins of the LM3102 as possible.

Refer to Layout Example, the loop formed by CIN, the main and synchronous MOSFET internal to the LM3102, and the PGND pin should be as small as possible. The connection from the PGND pin to CIN should be as short and direct as possible. Vias should be added to connect the ground of CIN to a ground plane, located as close to the capacitor as possible. The bootstrap capacitor CBST should be connected as close to the SW and BST pins as possible, and the connecting traces should be thick. The feedback resistors and capacitor RFB1, RFB2, and CFB should be close to the FB pin.

A long trace running from VOUT to RFB1 is generally acceptable because this is a low-impedance node. Ground RFB2 directly to the AGND pin (pin 7). The output capacitor COUT should be connected close to the load and tied directly to the ground plane. The inductor L should be connected close to the SW pin with as short a trace as possible to reduce the potential for EMI (electromagnetic interference) generation.

If it is expected that the internal dissipation of the LM3102 will produce excessive junction temperature during normal operation, making good use of the PCB ground plane can help considerably to dissipate heat. The exposed pad on the bottom of the LM3102 IC package can be soldered to the ground plane, which should extend out from beneath the LM3102 to help dissipate heat.

The exposed pad is internally connected to the LM3102 IC substrate. Additionally the use of thick traces, where possible, can help conduct heat away from the LM3102. Using numerous vias to connect the die attached pad to the ground plane is a good practice. Judicious positioning of the PCB within the end product, along with the use of any available air flow (forced or natural convection) can help reduce the junction temperature.