SNVS624B June   2011  – June 2016 LM3559

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements (SCL, SDA)
  7. 7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Amplifier Synchronization (TX1)
      2. 8.3.2  Input Voltage Flash Monitor Fault
      3. 8.3.3  Independent LED Control
      4. 8.3.4  Hardware Torch
      5. 8.3.5  Fault Protections
        1. 8.3.5.1 Overvoltage Protection
        2. 8.3.5.2 Current Limit
        3. 8.3.5.3 Flash Timeout
        4. 8.3.5.4 Indicator LED/Thermistor (LEDI/NTC)
          1. 8.3.5.4.1 Message Indicator Current Source (LEDI/NTC)
            1. 8.3.5.4.1.1 Message Indicator Example 1 (Single Pulse With Dead Time):
            2. 8.3.5.4.1.2 Message Indicator Example 2 (Multiple Pulses With Dead Time):
            3. 8.3.5.4.1.3 Updating The Message Indicator
      6. 8.3.6  Input Voltage (VIN ) Monitor
      7. 8.3.7  VIN Flash Monitor (Flash Current Rising)
      8. 8.3.8  Last Flash Register
      9. 8.3.9  LED Voltage Monitor
      10. 8.3.10 ADC Delay
      11. 8.3.11 Flags Register and Fault Indicators
        1. 8.3.11.1 Flash Timeout
        2. 8.3.11.2 Thermal Shutdown
        3. 8.3.11.3 LED Fault
        4. 8.3.11.4 TX1 and TX2 Interrupt Flags
        5. 8.3.11.5 LED Thermal Fault (NTC Flag)
        6. 8.3.11.6 Input Voltage Monitor Fault
    4. 8.4 Device Functional Modes
      1. 8.4.1  Start-Up (Enabling the Device)
      2. 8.4.2  Pass Mode
      3. 8.4.3  Flash Mode
      4. 8.4.4  Torch Mode
      5. 8.4.5  Privacy-Indicate Mode
      6. 8.4.6  GPIO1 Mode
      7. 8.4.7  TX2/INT/GPIO2
      8. 8.4.8  TX2 Mode
        1. 8.4.8.1 TX2 Shutdown
      9. 8.4.9  GPIO2 Mode
      10. 8.4.10 Interrupt Output (INT Mode)
      11. 8.4.11 NTC Mode
      12. 8.4.12 Alternate External Torch (AET Mode)
      13. 8.4.13 Automatic Conversion Mode
      14. 8.4.14 Manual Conversion Mode
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 START and STOP Conditions
        2. 8.5.1.2 I2C-Compatible Chip Address
        3. 8.5.1.3 Transferring Data
    6. 8.6 Register Maps
      1. 8.6.1  Enable Register
      2. 8.6.2  Torch Brightness Register
      3. 8.6.3  Flash Brightness Register
      4. 8.6.4  Flash Duration Register
      5. 8.6.5  Flags Register
      6. 8.6.6  Configuration Register 1
      7. 8.6.7  Configuration Register 2
      8. 8.6.8  GPIO Register
      9. 8.6.9  Last Flash Register
      10. 8.6.10 VLED Monitor Register
      11. 8.6.11 ADC Delay Register
      12. 8.6.12 Input Voltage Monitor Register
      13. 8.6.13 Privacy Register
      14. 8.6.14 Privacy PWM Period Register
      15. 8.6.15 Indicator Register
      16. 8.6.16 Indicator Blinking Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 LM3559 Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Capacitor Selection
          2. 9.2.1.2.2 Input Capacitor Selection
          3. 9.2.1.2.3 Inductor Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 LM3559 Typical Application Circuit With Thermistor
        1. 9.2.2.1 Detailed Design Procedure
          1. 9.2.2.1.1 NTC Thermistor Selection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN –0.3 6 V
VSCL, VSDA, VHWEN, VSTROBE, VTX1, VTX2, VLED1, VLED2, VLEDI/NTC –0.3 to the lesser of (VIN + 0.3 V) with 6 V maximum V
VSW, VOUT –0.3 6 V
Continuous power dissipation(2) Internally limited
Junction temperature, TJ-MAX 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typical) and disengages at TJ = 135°C (typical). Thermal shutdown is ensured by design.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage, VIN 2.5 5.5 V
Junction temperature, TJ –40 125 °C
Ambient temperature, TA(1) –40 85 °C
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).

6.4 Thermal Information

THERMAL METRIC(1) LM3559 UNIT
YZR (DSBGA)
16 PINS
RθJA Junction-to-ambient thermal resistance(2) 71.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.4 °C/W
RθJB Junction-to-board thermal resistance 9.8 °C/W
ψJT Junction-to-top characterization parameter 1.7 °C/W
ψJB Junction-to-board characterization parameter 1.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 9.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Junction-to-ambient thermal resistance (RθJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm × 76 mm × 1.6 mm with a 2 × 1 array of thermal vias. The ground plane on the board is 50 mm × 50 mm. Thickness of copper layers are 36 µm/18 µm/18 µm/36 µm (1.5 oz/1oz/1oz/1.5 oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1 W.

6.5 Electrical Characteristics

Unless otherwise specified, VIN = 3.6 V, VHWEN = VIN, TA = 25°C.(1) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT SOURCE SPECIFICATIONS
ILED Current source accuracy ILED1 + ILED2, 3 V ≤ VIN ≤ 4.2 V, VOUT = 4.5 V 900-mA flash current setting, per current source –7% 1800 7% mA
900-mA flash current setting, per current source
–40°C ≤ TA ≤ 85°C 		–4% 1800 4%
28.125-mA torch current, per current source –10% 56.2 10%
28.125-mA torch current, per current source
–40°C ≤ TA ≤ 85°C
VOUT – VLED1/2 Current source regulation voltage ILED = 1.8 A (ILED1 + ILED2), VOUT = 4.5 V 270 mV
VOVP Output overvoltage protection trip point(3) ON threshold 5 V
ON threshold, –40°C ≤ TA ≤ 85°C 4.925 5.075
OFF threshold 4.88
STEP-UP DC-DC CONVERTER SPECIFICATIONS
RPMOS PMOS switch on-resistance IPMOS = 1A 80 mΩ
RNMOS NMOS switch on-resistance INMOS = 1A 80 mΩ
ICL Switch current limit(4) 3 V ≤ VIN ≤ 4.2 V Flash Duration Register bits [6:5] = 00 1.4 A
3 V ≤ VIN ≤ 4.2 V
–40°C ≤ TA ≤ 85°C		 1.2 1.6
3 V ≤ VIN ≤ 4.2 V Flash Duration Register bits [6:5] = 01 2.1
3 V ≤ VIN ≤ 4.2 V
–40°C ≤ TA ≤ 85°C		 1.8 2.3
3 V ≤ VIN ≤ 4.2 V Flash Duration Register bits [6:5] = 10 2.7
3 V ≤ VIN ≤ 4.2 V
–40°C ≤ TA ≤ 85°C		 2.4 3
3 V ≤ VIN ≤ 4.2 V Flash Duration Register bits [6:5] = 11 3.2
3 V ≤ VIN ≤ 4.2 V
–40°C ≤ TA ≤ 85°C		 2.9 3.5
IOUT_SC Output short-circuit current limit VOUT < 2.3 V 350 mA
ILEDI/NTC Indicator current Register 0x12, bits[2:0] = 111, 2.7 V ≤ VIN ≤ 4.2 V
VLEDI/NTC = 2 V, –40°C ≤ TA ≤ 85°C		 18 mA
Register 0x12, bits[2:0] = 111, 2.7 V ≤ VIN ≤ 4.2 V
VLEDI/NTC = 2 V		 16 20
VTRIP Comparator trip threshold Configuration register 1, bit [4] = 1,
3 V ≤ VIN ≤ 4.2 V		 1 V
Configuration register 1, bit [4] = 1,
3 V ≤ VIN ≤ 4.2 V, –40°C ≤ TA ≤ 85°C		 0.97 1.03
ƒSW Switching frequency 2.7 V ≤ VIN ≤ 5.5 V 2 MHz
2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C 1.8 2.2
IQ Quiescent supply current Device not switching, VOUT = 3V 650 µA
Device switching, VOUT = 4.5V 1.55 mA
Indicate mode, Indicator Register bits [2:0] = 111
VLEDI/NTC = 2 V 		590 µA
Indicate mode, Indicator Register bits [2:0] = 111
VLEDI/NTC = 2 V, –40°C ≤ TA ≤ 85°C 		750
ISHDN Shutdown supply current 2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C HWEN = GND 1 µA
ISTBY Standby supply current 2.7 V ≤ VIN ≤ 5.5 V HWEN = VIN, Enable Register bits [1:0] = 00 1.25 µA
2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C 2.4
VIN_TH VIN monitor threshold VIN Monitor Register = 0x01 2.9 V
VIN Monitor Register = 0x01, –40°C ≤ TA ≤ 85°C 2.85 2.95
VIN_FLASH_TH VIN flash monitor threshold VIN Monitor Register = 0x08 2.9 V
VIN Monitor Register = 0x08, –40°C ≤ TA ≤ 85°C 2.85 2.95
tTX Flash-to-torch LED current settling time TX_ Low to High
ILED1 + ILED2 = 1.8A to 112.5mA		 20 µs
tD Time from when ILED hits target until VLED data is available ADC Delay Register bit [5] = 1 16 µs
ADC Delay Register bit [5] = 0
ADC Delay Register bits [4:0] = 0000		 250
VF_ADC ADC threshold VLED Monitor Register bits [3:0] = 1111 4.6 V
VLED Monitor Register bits [3:0] = 1111
–40°C ≤ TA ≤ 85°C		 4.4 4.8
HWEN, STROBE, TX1/TORCH/GPIO1, TX2/INT/GPIO2 VOLTAGE SPECIFICATIONS
VIL Input logic low 2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C 0 0.4 V
VIH Input logic high 2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C 1.2 VIN V
RPD Internal pulldown resistance on TX1, TX2, STROBE 300 kΩ
I2C-COMPATIBLE VOLTAGE SPECIFICATIONS (SCL, SDA)
VIL Input logic low 2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C 0 0.4 V
VIH Input logic high 2.7 V ≤ VIN ≤ 5.5 V 1.3 VIN V
VOL Output logic low (SDA) ILOAD = 3 mA
2.7 V ≤ VIN ≤ 5.5 V, –40°C ≤ TA ≤ 85°C		 0.4 V
(1) All voltages are with respect to the potential at the GND pin.
(2) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers represent the most likely norm. Unless otherwise stated, conditions for typical specifications are: VIN = 3.6 V and TA = 25°C.
(3) The typical curve for overvoltage protection (OVP) is measured in closed loop using Figure 43 . The OVP value is found by forcing an open circuit in the LED1 and LED2 path and recording the peak value of VOUT. The value given in Electrical Characteristics is found in an open loop configuration by ramping the voltage at OUT until the OVP comparator trips. The closed loop data can appear higher due to the stored energy in the inductor being dumped into the output capacitor after the OVP comparator trips. Worst case is an open circuit condition where the output voltage can continue to rise after the OVP comparator trips by approximately IIN × sqrt(L/COUT).
(4) The typical curve for current limit is measured in closed loop using Figure 43, and increasing IOUT until the peak inductor current stops increasing. The value given in Electrical Characteristics is measured open loop and is found by forcing current into SW until the current limit comparator threshold is reached. Closed loop data appears higher due to the delay between the comparator trip point and the NFET turning off. This delay allows the closed loop inductor current to ramp higher after the trip point by approximately 20 ns × VIN/L.

6.6 I2C Timing Requirements (SCL, SDA)

See(1)
MIN NOM MAX UNIT
1/t1 SCL(clock frequency) 400 kHz
t2 Data in setup time to SCL high 100 ns
t3 Data out stable after SCL low 0 ns
t4 SDA low setup time to SCL low (start) 100 ns
t5 SDA high hold time after SCL high (stop) 100 ns
(1) Specified by design, not production tested.