SNVSA52E August   2014  – September 2016 LM3644

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Flash Mode
      2. 8.3.2 Torch Mode
      3. 8.3.3 IR Mode
    4. 8.4 Device Functioning Modes
      1. 8.4.1 Start-Up (Enabling The Device)
      2. 8.4.2 Pass Mode
      3. 8.4.3 Power Amplifier Synchronization (TX)
      4. 8.4.4 Input Voltage Flash Monitor (IVFM)
      5. 8.4.5 Fault/Protections
        1. 8.4.5.1 Fault Operation
        2. 8.4.5.2 Flash Time-Out
        3. 8.4.5.3 Overvoltage Protection (OVP)
        4. 8.4.5.4 Current Limit
        5. 8.4.5.5 NTC Thermistor Input (Torch/Temp)
        6. 8.4.5.6 Undervoltage Lockout (UVLO)
        7. 8.4.5.7 Thermal Shutdown (TSD)
        8. 8.4.5.8 LED and/or VOUT Short Fault
    5. 8.5 Programming
      1. 8.5.1 Control Truth Table
      2. 8.5.2 I2C-Compatible Interface
        1. 8.5.2.1 Data Validity
        2. 8.5.2.2 Start and Stop Conditions
        3. 8.5.2.3 Transferring Data
        4. 8.5.2.4 I2C-Compatible Chip Address
    6. 8.6 Register Descriptions
      1. 8.6.1  Enable Register (0x01)
      2. 8.6.2  IVFM Register (0x02)
      3. 8.6.3  LED1 Flash Brightness Register (0x03)
      4. 8.6.4  LED2 Flash Brightness Register (0x04)
      5. 8.6.5  LED1 Torch Brightness Register (0x05)
      6. 8.6.6  LED2 Torch Brightness Register (0x06)
      7. 8.6.7  Boost Configuration Register (0x07)
      8. 8.6.8  Timing Configuration Register (0x08)
      9. 8.6.9  TEMP Register (0x09)
      10. 8.6.10 Flags1 Register (0x0A)
      11. 8.6.11 Flags2 Register (0x0B)
      12. 8.6.12 Device ID Register (0x0C)
      13. 8.6.13 Last Flash Register (0x0D)
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Capacitor Selection
        2. 9.2.2.2 Input Capacitor Selection
        3. 9.2.2.3 Inductor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Documentation
      1. 12.2.1 Related Links
      2. 12.2.2 Receiving Notification of Documentation Updates
      3. 12.2.3 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The high switching frequency and large switching currents of the LM3644 make the choice of layout important. The following steps should be used as a reference to ensure the device is stable and maintains proper LED current regulation across its intended operating voltage and current range.

  1. Place CIN on the top layer (same layer as the LM3644) and as close to the device as possible. The input capacitor conducts the driver currents during the low-side MOSFET turn-on and turn-off and can detect current spikes over 1 A in amplitude. Connecting the input capacitor through short, wide traces to both the IN and GND pins reduces the inductive voltage spikes that occur during switching which can corrupt the VIN line.
  2. Place COUT on the top layer (same layer as theLM3644) and as close as possible to the OUT and GND pin. The returns for both CIN and COUT should come together at one point, as close to the GND pin as possible. Connecting COUT through short, wide traces reduce the series inductance on the OUT and GND pins that can corrupt the VOUT and GND lines and cause excessive noise in the device and surrounding circuitry.
  3. Connect the inductor on the top layer close to the SW pin. There should be a low-impedance connection from the inductor to SW due to the large DC inductor current, and at the same time the area occupied by the SW node should be small so as to reduce the capacitive coupling of the high dV/dT present at SW that can couple into nearby traces.
  4. Avoid routing logic traces near the SW node so as to avoid any capacitively coupled voltages from SW onto any high-impedance logic lines such as TORCH/TEMP, STROBE, HWEN, SDA, and SCL. A good approach is to insert an inner layer GND plane underneath the SW node and between any nearby routed traces. This creates a shield from the electric field generated at SW.
  5. Terminate the Flash LED cathodes directly to the GND pin of the LM3644. If possible, route the LED returns with a dedicated path so as to keep the high amplitude LED currents out of the GND plane. For Flash LEDs that are routed relatively far away from the LM3644, a good approach is to sandwich the forward and return current paths over the top of each other on two layers. This helps reduce the inductance of the LED current paths.

11.2 Layout Example

LM3644 LM3644TT layout.gif Figure 63. Layout Example