SNVS053F June   2000  – September 2016 LM4140

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ON/OFF Operation
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Capacitors
      2. 8.1.2 Output Capacitors
      3. 8.1.3 Tantalum Capacitors
      4. 8.1.4 Aluminum Electrolytic Capacitors
      5. 8.1.5 Multilayer Ceramic Capacitors
      6. 8.1.6 Reverse Current Path
      7. 8.1.7 Output Accuracy
    2. 8.2 Typical Applications
      1. 8.2.1 Precision DAC Reference
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Boosted Output Current
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Boosted Output Current With Current Limiter
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
      4. 8.2.4 Complimentary Outputs
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
      5. 8.2.5 Voltage Reference With Force and Sense Output
        1. 8.2.5.1 Design Requirements
        2. 8.2.5.2 Detailed Design Procedure
      6. 8.2.6 Precision Programmable Current Source
        1. 8.2.6.1 Design Requirements
        2. 8.2.6.2 Detailed Design Procedure
      7. 8.2.7 Strain Gauge Conditioner for 350-Ω Bridge
        1. 8.2.7.1 Design Requirements
        2. 8.2.7.2 Detailed Design Procedure
      8. 8.2.8 Bipolar Voltage References for Low Power ADC
        1. 8.2.8.1 Design Requirements
        2. 8.2.8.2 Detailed Design Procedure
      9. 8.2.9 Self-Biased Low Power ADC Reference With Trim Current Sources
        1. 8.2.9.1 Design Requirements
        2. 8.2.9.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Maximum voltage on any input pin –0.3 5.6 V
Output short-circuit duration Indefinite
Power dissipation (TA = 25°C)(2) 345 mW
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Without PCB copper enhancements. The maximum power dissipation must be derated at elevated temperatures and is limited by TJMAX (maximum junction temperature), RθJA (junction to ambient thermal resistance) and TA (ambient temperature). The maximum power dissipation at any temperature is: PDissMAX = (TJMAX − TA)/RθJA up to the value listed in the Absolute Maximum Ratings. The RθJA for the 8-pin SOIC package is 160°C/W.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Ambient temperature 0 70 °C
Junction temperature 0 80 °C

6.4 Thermal Information

THERMAL METRIC(1) LM4140 UNIT
D (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance 119.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.3 °C/W
RθJB Junction-to-board thermal resistance 60.3 °C/W
ψJT Junction-to-top characterization parameter 14.5 °C/W
ψJB Junction-to-board characterization parameter 59.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

VIN = 3 V for the 1.024-V and 1.25-V, VIN = 5 V for all other voltage options, VEN = VIN, COUT = 1 µF(1), ILOAD = 1 mA, and
TA = TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
VREF Output voltage initial accuracy(4) All versions ±0.1%
TCVREF/°C Temperature coefficient 0°C ≤ TA ≤ 70°C A grade 3 ppm/°C
B grade 6
C grade 10
ΔVREF/ΔVIN Line regulation 1.024-V and 1.25-V options, 1.8 V ≤ VIN ≤ 5.5 V TA = 25°C 50 300 ppm/V
0°C ≤ TA ≤ 70°C 350
All other voltage options,
Vref + 200 mV ≤ VIN ≤ 5.5 V		 TA = 25°C 20 200
0°C ≤ TA ≤ 70°C 250
ΔVREF/ΔILOAD Load regulation 1 mA ≤ ILOAD ≤ 8 mA All other voltage options TA = 25°C 1 20 ppm/mA
0°C ≤ TA ≤ 70°C 150
4.096-V option TA = 25°C 5 35
0°C ≤ TA ≤ 70°C 150
ΔVREF Long-term stability 1000 hours 60 ppm
ΔVREF Thermal hysteresis(5) 0°C ≤ TA ≤ + 70°C 20 ppm
Operating voltage 1.024-V and 1.25-V options, IL = 1 mA to 8 mA, 0°C ≤ TA ≤ 70°C 1.8 5.5 V
VIN-VREF Dropout voltage(6) 2.048-V and 2.5-V options IL = 1 mA TA = 25°C 20 40 mV
0°C ≤ TA ≤ 70°C 45
IL = 8 mA TA = 25°C 160 235
0°C ≤ TA ≤ 70°C 400
4.096-V option IL = 1 mA TA = 25°C 20 40
0°C ≤ TA ≤ 70°C 45
IL = 8 mA TA = 25°C 195 270
0°C ≤ TA ≤ 70°C 490
VN Output noise voltage(7) 0.1 Hz to 10 Hz 2.2 µVPP
IS(ON) Supply current ILOAD = 0 mA All other voltage options TA = 25°C 230 320 µA
0°C ≤ TA ≤ 70°C 375
4.096-V option TA = 25°C 265 350
0°C ≤ TA ≤ 70°C 400
IS(OFF) Supply current VEnable < 0.4 V TA = 25°C 0.01 µA
0°C ≤ TA ≤ 70°C 1
VH Logic high input voltage 0°C ≤ TA ≤ 70°C 0.8 × VIN V
IH Logic high input current 2 nA
VL Logic low input voltage 0°C ≤ TA ≤ 70°C 0.4 V
IL Logic low input current 1 nA
ISC Short-circuit current TA = 25°C 8.5 20 35 mA
0°C ≤ TA ≤ 70°C 40
(1) For proper operation, a 1-µF capacitor is required between the output pin and the GND pin of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).
(3) Typical numbers are at 25°C and represent the most likely parametric norm.
(4) High temperature and mechanical stress associated with PCB assembly can have significant impact on the initial accuracy of the LM4140 and may create significant shifts in VREF.
(5) Thermal hysteresis is defined as the changes in 25°C output voltage before and after the cycling of the device from 0°C to 70°C.
(6) Dropout voltage is defined as the minimum input to output differential voltage at which the output voltage drops by 0.5% below the value measured with VIN = 3 V for the 1.024-V and 1.25-V, VIN = 5 V for all other voltage options.
(7) The output noise is based on 1.024 V option. Output noise is linearly proportional to VREF.

6.6 Typical Characteristics

TA = 25°C, no load, COUT = 1 µF, VIN = 3 V for 1.024-V and 1.25-V, and 5 V for all other voltage options, and VIN = VEN (unless otherwise noted). The 1-µF output capacitor is actively discharged to ground (see ON/OFF Operation for more details).
LM4140 10107905.png Figure 1. Power Up and Down Ground Current
LM4140 10107907.png Figure 3. Line Transient Response
LM4140 10107909.png Figure 5. Output Impedance
LM4140 10107911.png
1.024-V and 1.25-V options require 1.8-V supply
Figure 7. Dropout Voltage vs Load Current
LM4140 10107913.png Figure 9. Total Current (IS(OFF)) vs Supply Voltage
LM4140 10107931.png Figure 11. Spectral Noise Density (0.1 Hz to 10 Hz)
LM4140 10107938.png Figure 13. Ground Current vs Load Current
LM4140 10107940.png Figure 15. Load Regulation vs Temperature
LM4140 10107942.png Figure 17. Line Regulation vs Temperature
LM4140 10107944.png Figure 19. Short-Circuit Current vs Temperature
LM4140 10107923.png Figure 21. Typical Temperature Coefficient (Sample of 5 Parts)
LM4140 10107906.png Figure 2. Enable Response
LM4140 10107908.png Figure 4. Load Transient Response
LM4140 10107910.png Figure 6. Power Supply Rejection Ratio
LM4140 10107912.png Figure 8. Output Voltage Change vs Sink Current (ISINK)
LM4140 10107914.png Figure 10. Total Current (IS(ON)) vs Supply Voltage
LM4140 10107932.png Figure 12. Spectral Noise Density (10 Hz to 100 kHz)
LM4140 10107939.png Figure 14. Long-Term Drift
LM4140 10107941.png Figure 16. Output Voltage vs Load Current
LM4140 10107943.png Figure 18. IQ vs Temperature
LM4140 10107945.png Figure 20. Dropout Voltage vs Load Current (VOUT) = 2 V