SNVSA09D April 2014 – August 2017 LM43603
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LM43603 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 3 A. The following design procedure can be used to select components for the LM43603. Alternately, the WEBENCH® software may be used to generate complete designs. When generating a design, the WEBENCH^{®} software utilizes iterative design procedure and accesses comprehensive databases of components. Please go to ti.com for more details.
This section presents a simplified discussion of the design process.
The LM43603 only requires a few external components to convert from a wide voltage range supply to a fixed output voltage. Figure 46 shows a basic schematic when BIAS is connected to V_{OUT} and this is recommended for V_{OUT} ≥ 3.3 V. For V_{OUT} < 3.3 V, BIAS should be connected to ground, as shown in Figure 47.
The LM43603 also integrates a full list of optional features to aid system design requirements such as precision enable, V_{CC} UVLO, programmable soft-start, output voltage tracking, programmable switching frequency, clock synchronization and power-good indication. Each application can select the features for a more comprehensive design. A schematic with all features utilized is shown in Figure 48.
The external components have to fulfill the needs of the application, but also the stability criteria of the device's control loop. The LM43603 is optimized to work within a range of external components. The LC output filter's inductance and capacitance have to be considered in conjunction, creating a double pole, responsible for the corner frequency of the converter. Table 2 can be used to simplify the output filter component selection.
F_{S} (kHz) | V_{OUT} (V) | L (µH)^{(2)} | C_{OUT} (µF) ^{(1)} | C_{FF} (pF) ^{(3)}^{(4)} | R_{T} (kΩ) | R_{FBB} (kΩ) ^{(3)}^{(4)} |
---|---|---|---|---|---|---|
200 | 1 | 4.8 | 600 | none | 200 | 100 |
500 | 1 | 2.2 | 400 | none | 80.6 or open | 100 |
1000 | 1 | 1 | 250 | none | 39.2 | 100 |
2200 | 1 | 0.47 | 150 | none | 17.8 | 100 |
200 | 3.3 | 15 | 300 | 47 | 200 | 432 |
500 | 3.3 | 4.7 | 150 | 33 | 80.6 or open | 432 |
1000 | 3.3 | 3.3 | 100 | 22 | 39.2 | 432 |
2200 | 3.3 | 1 | 50 | 18 | 17.8 | 432 |
200 | 5 | 18 | 200 | 68 | 200 | 249 |
500 | 5 | 6.8 | 120 | 44 | 80.6 or open | 249 |
1000 | 5 | 3.3 | 100 | 33 | 39.2 | 249 |
2200 | 5 | 1.5 | 50 | 22 | 17.8 | 249 |
200 | 12 | 33 | 100 | See note^{(5)} | 200 | 90.9 |
500 | 12 | 15 | 50 | 68 | 80.6 or open | 90.9 |
1000 | 12 | 6.8 | 44 | 56 | 39.2 | 90.9 |
200 | 24 | 44 | 47 | See note^{(5)} | 200 | 43.2 |
500 | 24 | 18 | 47 | See note^{(5)} | 80.6 or open | 43.2 |
1000 | 24 | 10 | 33 | See note^{(5)} | 39.2 | 43.2 |
Detailed design procedure is described based on a design example. For this design example, use the parameters listed in Table 3 as the input parameters.
DESIGN PARAMETER | VALUE |
---|---|
Input Voltage V_{IN} | 12 V typical, range from 3.5 V to 36 V |
Output Voltage V_{OUT} | 3.3 V |
Input Ripple Voltage | 400 mV |
Output ripple voltage | 30 mV |
Output Current Rating | 3 A |
Operating Frequency | 500 kHz |
Soft-start time | 10 ms |
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The output voltage of the LM43603 device is externally adjustable using a resistor divider network. The divider network is comprised of top feedback resistor R_{FBT} and bottom feedback resistor R_{FBB}. The following equation is used to determine the output voltage of the converter:
Choose the value of the R_{FBT} to be 1 MΩ to minimize quiescent current to improve light load efficiency in this application. With the desired output voltage set to be 3.3 V and the V_{FB} = 1.011 V, the R_{FBB} value can then be calculated using Equation 11. The formula yields a value of 434.78 kΩ. Choose the closest available value of 432 kΩ for the R_{FBB}. Please refer to Adjustable Output Voltage for more details.
The default switching frequency of the LM43603 device is set at 500 kHz when RT pin is open circuit. The switching frequency is selected to be 500 kHz in this application for one less passive components. If other frequency is desired, use Equation 12 to calculate the required value for R_{T}.
For 500 kHz, the calculated R_{T} is 79.8 kΩ and standard value 80.6 kΩ can also be used to set the switching frequency at 500 kHz.
The LM43603 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor, depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7 µF to 10 µF. A high-quality ceramic type X5R or X7R with sufficiency voltage rating is recommended. The voltage rating must be greater than the maximum input voltage. To compensate the derating of ceramic capactors, a voltage rating of twice the maximum input voltage is recommended. Additionally, some bulk capacitance can be required, especially if the LM43603 circuit is not located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to the voltage spiking due to the lead inductance of the cable or trace. The value for this capacitor is not critical but must be rated to handle the maximum input voltage including ripple. For this design, a 10 µF, X7R dielectric capacitor rated for 100 V is used for the input decoupling capacitor. The equivalent series resistance (ESR) is approximately 3 mΩ, and the current-rating is 3 A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close as possible to the device pins.
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will have a strong influence on the final effective capacitance. Therefore the right capacitor value has to be chosen carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance.
The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is based on the desired peak-to-peak ripple current, Δi_{L}, that flows in the inductor along with the DC load current. As with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance gives lower ripple current and hence lower output voltage ripple with the same output capacitors. Lower inductance could result in smaller, less expensive component. An inductance that gives a ripple current of 20% to 40% of the 3 A at the typical supply voltage is a good starting point. Δi_{L} = (1/5 to 2/5) x I_{OUT}. The peak-to-peak inductor current ripple can be found by Equation 13 and the range of inductance can be found by Equation 14 with the typical input voltage used as V_{IN}.
D is the duty cycle of the converter where in a buck converter case it can be approximated as D = V_{OUT} / V_{IN}, assuming no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductance value will come out in micro Henries. The inductor ripple current ratio is defined by:
The second criterion is inductor saturation current rating. The inductor should be rated to handle the maximum load current plus the ripple current:
The LM43603 has both valley current limit and peak current limit. During an instantaneous short, the peak inductor current can be high due to a momentary increase in duty cycle. The inductor current rating should be higher than the HS current limit. It is advised to select an inductor with a larger core saturation margin and preferably a softer roll off of the inductance value over load current.
In general, it is preferable to choose lower inductance in switching power supplies, because it usually corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low of an inductance can generate too large of an inductor current ripple such that over current protection at the full load could be falsely triggered. It also generates more conduction loss, since the RMS current is slightly higher relative that with lower current ripple at the same DC current. Larger inductor current ripple also implies larger output voltage ripple with the same output capacitors. With peak current mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current ripple improves the comparator signal to noise ratio.
Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. The ‘hard’ saturation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate!
For the design example, a standard 6.8 μH inductor from Wurth Elektronik, Coilcraft, or Vishay can be used for the 3.3 V output with plenty of current rating margin.
The device is designed to be used with a wide variety of LC filters. It is generally desired to use as little output capacitance as possible to keep cost and size down. The output capacitor (s), COUT, should be chosen with care since it directly affects the steady state output voltage ripple, loop stability and the voltage over/undershoot during load current transients.
The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the Equivalent Series Resistance (ESR) of the output capacitors:
The other is caused by the inductor current ripple charging and discharging the output capacitors:
The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of the two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rates. When a fast large load transient happens, output capacitors provide the required charge before the inductor current can slew to the appropriate level. The initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop until the control loop response increases or decreases the inductor current to supply the load. To maintain a small over- or undershoot during a transient, small ESR and large capacitance are desired. But these also come with higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output voltage deviation.
For a given input and output requirement, the following inequality gives an approximation for an absolute minimum output cap required:
Along with this for the same requirement, the max ESR should be calculated as per the following inequality
where
r = Ripple ratio of the inductor ripple current (ΔI_{L} / I_{OUT})
ΔV_{OUT} = Target output voltage undershoot
D’ = 1 – Duty cycle
F_{S} = Switching Frequency
I_{OUT} = Load Current
A general guide line for C_{OUT} range is that C_{OUT} should be larger than the minimum required output capacitance calculated by Equation 19, and smaller than 10 times the minimum required output capacitance or 1 mF. In applications with V_{OUT} less than 3.3 V, it is critical that low ESR output capacitors are selected. This will limit potential output voltage overshoots as the input voltage falls below the device normal operating range. To optimize the transient behavior a feed-forward capacitor could be added in parallel with the upper feedback resistor. For this design example, three 47 µF,10 V, X7R ceramic capacitors are used in parallel.
The LM43603 is internally compensated and the internal R-C values are 400 kΩ and 50 pF respectively. Depending on the V_{OUT} and frequency F_{S}, if the output capacitor C_{OUT} is dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor C_{FF} can be added in parallel with R_{FBT}. C_{FF} is chosen such that phase margin is boosted at the crossover frequency without C_{FF}. A simple estimation for the crossover frequency without C_{FF} (f_{x}) is shown in Equation 21, assuming C_{OUT} has very small ESR.
The following equation for C_{FF} was tested:
This equation indicates that the crossover frequency is geometrically centered on the zero and pole frequencies caused by the C_{FF} capacitor.
For designs with higher ESR, C_{FF} is not neeed when C_{OUT} has very high ESR and C_{FF} calculated from Equation 22 should be reduced with medium ESR. Table 2 can be used as a quick starting point.
For the application in this design example, a 47 pF COG capacitor is selected.
Every LM43603 design requires a bootstrap capacitor, C_{BOOT}. The recommended bootstrap capacitor is 0.47 μF and rated at 6.3 V or higher. The bootstrap capacitor is located between the SW pin and the CBOOT pin. The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.
The VCC pin is the output of an internal LDO for LM43603. The input for this LDO comes from either VIN or BIAS (please refer to Functional Block Diagram for LM43603). To insure stability of the part, place a minimum of 2.2 µF, 10 V capacitor for this pin to ground.
For an output voltage of 3.3 V and greater, the BIAS pin can be connected to the output in order to increase light load efficiency. This pin is an input for the VCC LDO. When BIAS is not connected, the input for the VCC LDO will be internally connected into VIN. Since this is an LDO, the voltage differences between the input and output will affect the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be added close to the BIAS pin as an input capacitor for the LDO.
The user can left the SS/TRK pin floating and the LM43603 will implement a soft start time of 4.1 ms typically. In order to use an external soft start capacitor, the capacitor should be sized such that the soft start time will be longer than 4.1 ms. Use the following equation in order to calculate the soft start capacitor value:
Where,
C_{SS} = Soft start capacitor value (µF)
I_{SS} = Soft start charging current (µA)
t_{SS} = Desired soft start time (s)
For the desired soft start time of 10 ms and soft start charging current of 2.0 µA, the equation above yield a soft start capacitor value of 0.020 µF.
The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R_{ENT} and R_{ENB}. R_{ENT} is connected between the VIN pin and the EN pin of the LM43603. R_{ENB} is connected between the EN pin and the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. The following equation can be used to determine the VIN UVLO level.
The EN rising threshold (V_{ENH}) for LM43603 is set to be 2.2 V (typical). Choose the value of R_{ENB} to be 1 MΩ to minimize input current from the supply. If the desired VIN UVLO level is at 5.0 V, then the value of R_{ENT} can be calculated using the equation below:
The above equation yields a value of 1.27 MΩ. The resulting falling UVLO threshold, equals 4.3 V, can be calculated by below equation, where EN falling threshold (V_{ENL}) is 1.9 V (typical).
A typical pull-up resistor value is 10 kΩ to 100 kΩ from PGOOD pin to a voltage no higher than 12 V. If it is desired to pull up PGOOD pin to a voltage higher than 12 V, a resistor can be added from PGOOD pin to ground to divide the voltage seen by the PGOOD pin to a value no higher than 12 V.
V_{OUT} = 1 V | F_{S} = 500 kHz |
V_{OUT} = 1 V | F_{S} = 500 kHz |
V_{IN} = 12 V | V_{OUT} = 1 V |
V_{OUT} = 3.3 V | F_{S} = 500 kHz |
V_{OUT} = 3.3 V | F_{S} = 500 kHz |
V_{OUT} = 3.3 V | F_{S} = 500 kHz |
V_{OUT} = 3.3 V | F_{S} = 500 kHz |
V_{OUT} = 3.3 V | F_{S} = 500 kHz |
V_{OUT} = 3.3 V | F_{S} = 500 kHz |
V_{OUT} = 5 V | F_{S} = 200 kHz |
V_{OUT} = 5 V | F_{S} = 200 kHz |
V_{OUT} = 5 V | F_{S} = 200 kHz |
V_{OUT} = 5 V | F_{S} = 500 kHz |
V_{OUT} = 5 V | F_{S} = 500 kHz |
V_{OUT} = 5 V | F_{S} = 500 kHz |
V_{OUT} = 5 V | F_{S} = 1 MHz |
V_{OUT} = 5 V | F_{S} = 1 MHz |
V_{OUT} = 5 V | F_{S} = 1 MHz |
V_{OUT} = 5 V | F_{S} = 2.2 MHz |
V_{OUT} = 5 V | F_{S} = 2.2 MHz |
V_{OUT} = 5 V | F_{S} = 2.2 MHz |
V_{OUT} = 12 V | F_{S} = 500 kHz |
V_{OUT} = 12 V | F_{S} = 500 kHz |
V_{OUT} = 12 V | F_{S} = 500 kHz | V_{IN} = 24 V |
V_{OUT} = 1 V | Fs = 500 kHz |
V_{OUT} = 1 V | F_{S} = 500 kHz |
V_{OUT} = 1 V | F_{S} = 500 kHz | θ_{JA} = 20°C/W |
V_{OUT} = 3.3 V | F_{S} = 500 kHz |
V_{OUT} = 3.3 V | F_{S} = 500 kHz |
V_{OUT} = 3.3 V | F_{S} = 500 kHz |
V_{OUT} = 3.3 V | F_{S} = 500 kHz |
V_{OUT} = 3.3 V | F_{S} = 500 kHz |
V_{OUT} = 3.3 V | F_{S} = 500 kHz | θ_{JA} = 20°C/W |
V_{OUT} = 5 V | F_{S} = 200 kHz |
V_{OUT} = 5 V | F_{S} = 200 kHz |
V_{OUT} = 5 V | F_{S} = 200 kHz | θ_{JA} = 20°C/W |
V_{OUT} = 5 V | F_{S} = 500 kHz |
V_{OUT} = 5 V | F_{S} = 500 kHz |
V_{OUT} = 5 V | F_{S} = 500 kHz | θ_{JA} = 20°C/W |
V_{OUT} = 5 V | F_{S} = 1 MHz |
V_{OUT} = 5 V | F_{S} = 1 MHz |
V_{OUT} = 5 V | F_{S} = 1 MHz | θ_{JA} = 20°C/W |
V_{OUT} = 5 V | F_{S} = 2.2 MHz |
V_{OUT} = 5 V | F_{S} = 2.2 MHz |
V_{OUT} = 5 V | F_{S} = 2.2 MHz | θ_{JA} = 20°C/W |
V_{OUT} = 12 V | F_{S} = 500 kHz |
V_{OUT} = 12 V | F_{S} = 500 kHz |
V_{OUT} = 12 V | F_{S} = 500 kHz | θ_{JA} = 20°C/W |