SNAS470E October 2008 – November 2015 LM48100Q-Q1
The LM48100Q-Q1 integrates a comprehensive output fault detection system, which can sense the load conditions, protecting the device during short circuit events and detecting open circuit conditions. High power supply rejection ratio allows the device to operate in noisy environments without additional power supply conditioning. Dual audio inputs can be mixed or multiplexed to the device output. Each input path has its own independent, 32-step volume control. The mixer, volume control and device mode select are controlled through an I2C compatible interface. An open drain FAULT output indicates when a fault has occurred. Comprehensive output short circuit and thermal overload protection prevent the device from damage during fault conditions. Superior click and pop suppression eliminates audible transients on power-up, power-down, and during shutdown.
The LM48100Q-Q1 output fault diagnostics are controlled through the I2C interface. When power is initially applied to the device, the LM48100Q-Q1 initializes, performing the full diagnostic sequence; output short to VDD and GND, outputs shorted together, and no load condition, is performed. The device remains in shutdown while the initial diagnostic check is performed. Any I2C commands written to the device during this time are stored and implemented once the diagnostic check is complete. The initial diagnostic sequence can be terminated by setting DG_RESET = 1.
The Diagnostic Control register, register 1, controls the LM48100Q-Q1 diagnostic process. Bit B4, DG_EN, enables the output fault detection. Set DG_EN = 1 to enable the output diagnostic test sequence. The LM48100Q-Q1 treats the DG_EN bit as rising-edge-sensitive; once DG_EN = 1 is clocked into the device, the diagnostic test is performed. If the LM48100Q-Q1 is in one-shot mode, once the test sequence is performed, the DG_EN bit is ignored and the test sequence will not be run again. Cycle DG_EN from high-to-low-to-high to re-enable the one-shot diagnostic test sequence.
In continuous diagnostic mode, the test sequence is repeated until either a fault condition occurs, DG_RESET is cycled, or the device is taken out of continuous diagnostic mode. Set DG_CONT = 1 before setting DG_EN = 1 to initiate a continuous diagnostic. Set DG-CONT = 0 to disable continuous diagnostic mode. When the device is active and DG_EN = 0, the LM48100Q-Q1 does not perform the output short, or no load diagnostics, however, the thermal overload and output over current protection circuitry remains active, and disables the device should a thermal or over-current fault occur. The initial diagnostic operation when power is applied to the device occurs regardless of the state of DG_EN. The LM48100Q-Q1 output fault detection can be set to either continuous mode where the output diagnostic occurs every 60ms, or a one-shot mode. Set bit B3 (DG_CONT) to 1 for continuous mode, set B3 = 0 for one-shot mode.
Bit B2, DG_RESET, restores the LM48100Q-Q1 to normal operation after an output fault is detected. Toggle DG_RESET to re-enable the device outputs and set FAULT high.
|B1||ILIMIT||0||Fixed output current limit|
|1||Supply dependent output current limit|
|0||Normal operation. FAULT remains low and device is disabled once a fault occurs.|
|1||Reset FAULT output. Device returns to pre-fault operation.|
|0||One shot diagnostic|
The LM48100Q-Q1 output fault tests are individually controlled through the Fault Detection Control register, register 2. Setting any of the bits in the Fault Detection Control register to 1 causes the FAULT circuitry to ignore the associated test. For example, if B2 (RAIL_SHT) = 1 and the output is shorted to VDD, the FAULT output remains high. Although the FAULT circuitry ignores the selected test, the LM48100Q-Q1 protection circuitry remains active, and disables the device. This feature is useful for diagnosing which fault caused a FAULT condition.
If DG_EN = 1, and a diagnostic sequence is initiated, all the tests are performed regardless of their state in the Fault Detection Control register. If DG_EN = 0, the RAIL_SHT, OUTPUT_OPEN and OUTPUT_SHT tests are not performed, however, the thermal overload and output over-current detection circuitry remains active.
|1||Ignore output short circuit fault (outputs shorted together)|
|1||Ignore output short circuit fault|
|1||Ignore output short to VDD or GND fault|
|1||Ignore output over-current fault|
|1||Ignore thermal overload fault|
The LM48100Q-Q1 is designed to drive a load differentially, a configuration commonly referred to as a bridge-tied load (BTL). The BTL configuration differs from the single-ended configuration, where one side of the load is connected to ground. A BTL amplifier offers advantages over a single-ended device. By driving the load differentially, the output voltage is doubled, compared to a single-ended amplifier under similar conditions. This doubling of the output voltage leads to a quadrupling of the output power. For example, the theoretical maximum output power for a single-ended amplifier driving 8 Ω and operating from a 5 V supply is 158 mW, while the theoretical maximum output power for a BTL amplifier operating under the same conditions is 633 mW. Since the amplifier outputs are both biased about VDD/2, there is no net DC voltage across the load, eliminating the DC blocking capacitors required by single-ended, single-supply amplifiers.
The LM48100Q-Q1 features an input mixer/multiplexer controlled through the I2C interface. The mixer/multiplexer allows either input, or the combination of both inputs to appear at the device output. Bits B2 (INPUT_1) and B3 (INPUT_2) of the Mode Control Register select the individual input channels. Set INPUT_1 = 1 to select the audio signal on IN1. Set INPUT_2 = 1 to select the audio signal on IN2. Setting both INPUT_1 and INPUT_2 = 1 mixes VIN1 and VIN2, and the LM48100Q-Q1 outputs the result as a mono signal (Table 3).
|0||0||MUTE. No input selected|
|1||1||IN1 + IN2|
With a standard speaker load (6 Ω to 100 Ω) connected between OUTA and OUTB, the LM48100Q-Q1 can detect a short between the outputs and either VDD or GND. A short is detected if the impedance between either OUTA or OUTB and VDD or GND is less than 3 kΩ. A short is also detected if the impedance between BOTH OUTA and OUTB and either VDD or GND is less than 6 kΩ. Under either of these conditions, the amplifier outputs are disabled and FAULT is driven low. No short is detected if the impedance between either output and VDD or GND is greater than 7.5 kΩ. Likewise, no short is detected if the impedance between BOTH outputs and VDD or GND is greater than 15 kΩ.
The LM48100Q-Q1 can detect whether the amplifier outputs have been shorted together or, an output open circuit condition has occurred. An output short circuit is detected if the impedance between OUTA and OUTB is less than 2 Ω. An open circuit is detected if the impedance between OUTA and OUTB is greater than 200 Ω. Under either of these conditions, the amplifier outputs are disabled and FAULT is driven low. The device remains in normal operation if the impedance between OUTA and OUTB is in the range of 6 Ω to 100 Ω. The output open circuit test is only performed during the initial diagnostic sequence during power up, or when DG_ENABLE is set to 1.
The LM48100Q-Q1 has two over current detection modes, a fixed current limit, and a supply dependent current limit. Bit B1 (ILIMIT) of the Diagnostic Control Register selects the over-current detection mode. Set ILIMIT = 0 to select a fixed current limit of 1.47 A (typ). Set ILIMIT = 1 to select the supply dependent current limit mode. In supply dependent mode, the current limit is determined by Equation 1:
If the output current exceeds the current limit, the device outputs are disabled and FAULT is driven low. The output over-current detection circuitry remains active when the diagnostics have been disabled (DG_EN = 0).
The LM48100Q-Q1 has thermal overload threshold of 170 °C (typ). If the die temperature exceeds 170 °C, the outputs are disabled and FAULT is driven low. The thermal overload detection circuitry remains active when the diagnostics have been disabled (DG_EN = 0).
The LM48100Q-Q1 features an open drain, fault indication output, FAULT , that asserts when a fault condition is detected by the device. FAULT goes low when either an output short, output open, over current, or thermal overload fault is detected, and the diagnostic test is not ignored, see Fault Detection Control Register section. FAULT remains low even after the fault condition has been cleared and the diagnostic tests are repeated. Toggle DG_RESET to clear FAULT.
Connect a 1.5-kΩ or higher pullup resistor between FAULT and VDD.
|VOLUME STEP||VOL4||VOL3||VOL2||VOL1||VOL0||GAIN (dB)|
The LM48100Q-Q1 features an I2C selectable low power shutdown mode that disables the device, reducing quiescent current consumption to 0.01 μA. Set bit B4 (POWER_ON) in the Mode Control Register to 0 to disable the device. Set B0 to 1 to enable the device.
The increase in power delivered by a BTL amplifier leads to a direct increase in internal power dissipation. The maximum power dissipation for a BTL amplifier for a given supply voltage and load is given by Equation 2:
The maximum power dissipation of the HTSSOP package is calculated by Equation 3:
If the power dissipation for a given operating condition exceeds the package maximum, either decrease the ambient temperature, increase air flow, add heat sinking to the device, or increase the load impedance and/or supply voltage. The LM48100Q-Q1 HTSSOP package features an exposed die attach pad (DAP) that can be used to increase the maximum power dissipation of the package, see Exposed DAP Mounting Considerations.
The LM48100Q-Q1 features thermal overload protection that disables the amplifier output stage when the die temperature exceeds 170 °C. See the Thermal Overload Detection section.
The LM48100Q-Q1 output fault diagnostics support two different modes: one-shot mode and continuous diagnostic mode.
If the LM48100Q-Q1 is in one-shot mode, once the test sequence is performed, the DG_EN bit is ignored and the test sequence will not be run again.
In continuous diagnostic mode, the test sequence is repeated until either a fault condition occurs, DG_RESET is cycled, or the device is taken out of continuous diagnostic mode.
The LM48100Q-Q1 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM48100Q-Q1 and the master can communicate at clock rates up to 400 kHz. Figure 12 shows the I2C interface timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48100Q-Q1 is a transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition (Figure 13). Each data word, device address and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 14). The LM48100Q-Q1 device address is 111110X, where X is determined by ADR (Table 6). ADR = 1 sets the device address to 1111101. ADR = 0 sets the device address to 1111100.
The I2C bus format is shown in Figure 14. The START signal, the transition of SDA from HIGH to LOW while SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0 indicates the master is writing to the slave device, RW = 1 indicates the master wants to read data from the slave device. Set R/W = 0; the LM48100Q-Q1 is a WRITE-ONLY device and will not respond the R/W = 1. The data is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM48100Q-Q1 receives the correct address, the device pulls the SDA line low, generating an acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable while SCL is HIGH. After the 8-bit register data word is sent, the LM48100Q-Q1 sends another ACK bit. Following the acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high.
|ADR = 0||1||1||1||1||1||0||0||0|
|ADR = 1||1||1||1||1||1||0||1||0|
|2||FAULT DETECTION CONTROL||0||1||0||TSD||OCF||RAIL_SHT||OUTPUT
|3||VOLUME CONTROL 1||0||1||1||VOL1_4||VOL1_3||VOL1_2||VOL1_1||VOL1_0|
|4||VOLUME CONTROL 2||1||0||0||VOL2_4||VOL2_3||VOL2_2||VOL_2||VOL2_0|
|B2||INPUT_1||0||IN1 Input unselected|
|1||IN1 Input selected|
|B3||INPUT_2||0||IN2 Input unselected|
|1||IN2 Input selected|