SNVS961E APRIL   2013  – January 2016 LM5023

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 QR Pin
        2. 7.3.1.2 VSD Pin
        3. 7.3.1.3 SS Pin
        4. 7.3.1.4 COMP Pin
        5. 7.3.1.5 CS Pin
        6. 7.3.1.6 GND Pin
        7. 7.3.1.7 OUT Pin
        8. 7.3.1.8 VCC Pin
      2. 7.3.2 Start-Up
      3. 7.3.3 Quasi-Resonant Operation
      4. 7.3.4 Quasi-Resonant Operating Frequency
      5. 7.3.5 PWM Comparator
      6. 7.3.6 Soft-Start
      7. 7.3.7 Gate Driver
        1. 7.3.7.1 Skip-Cycle Operation
      8. 7.3.8 Current Limit and Current Sense
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design with WEBENCH Tools
        2. 8.2.2.2 Line Current-Limit Feedforward
          1. 8.2.2.2.1 Overvoltage Protection
        3. 8.2.2.3 Valley Switching
        4. 8.2.2.4 Hiccup Mode
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Custom Design with WEBENCH Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM5023 is a quasi-resonant PWM controller optimized for isolated flyback converters with secondary-side regulation. The controller can be used with single or multiple output converters. Applications include notebook adapters and a variety of consumer and industrial applications. The skip-cycle operation, reduced device bias current and control for high-voltage start-up circuit facilitates achieving low-standby input power.

8.2 Typical Application

This AC-to-DC adapter, 19.2-V, 65-W design example describes the design of a 65-W off-line flyback converter providing 19.2 V at 3.43-A maximum load and operating from a universal AC input. The design uses the LM5023 AC-to-DC quasi-resonant primary-side controller in a DCM type flyback converter and achieves 88% full load efficiency.

LM5023 snvs961_schem.gif Figure 13. LM5023 Typical Application

8.2.1 Design Requirements

Table 1 lists the design requirements for the LM5023.

Table 1. LM5023 Performance Specifications

PARAMETER TEST CONDITION MIN TYP MAX UNITS
INPUT CHARACTERISTICS
VIN Input voltage 90 115/230 264 VAC
VIN No load input power VIN = 230 V 30 mW
OUTPUT CHARACTERISTICS
VOUT Output voltage VIN = 115 V, IOUT = 3.43 A 19.0 19.2 19.4 V
VOUT Line regulation VIN = min to max, IOUT = max 1.0%
VOUT Load regulation VIN = nom, IOUT = no load to max load 1.0%
VOUT Output voltage ripple VIN = nom, IOUT = max load 100 mVPP
IOUT Output current 3.43 A
VOVP Output OVP 24 V
M Load step response IOUT = 0.343 A to 3.09 A, 3.09 A to 0.343 A 18.7 19.6 V
SYSTEMS CHARACTERISTICS
Switching frequency 130 kHz
η Full load VIN = 115/230 V, IOUT = 3.43 A 88%

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design with WEBENCH Tools

Click here to create a custom design using the LM5023 device with the WEBENCH® Power Designer.

  1. Start by entering your VIN, VOUT and IOUT requirements.
  2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments.
  3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability.
  4. In most cases, you will also be able to:
    • Run electrical simulations to see important waveforms and circuit performance,
    • Run thermal simulations to understand the thermal performance of your board,
    • Export your customized schematic and layout into popular CAD formats,
    • Print PDF reports for the design, and share your design with colleagues.
  5. Get more information about WEBENCH tools at www.ti.com/webench.

8.2.2.2 Line Current-Limit Feedforward

In a peak-current mode controlled when the power supply is in an overload, the peak current (measured across the current sense resistor VCS) is compared to a voltage reference for overload protection. If the peak current exceeds the reference the LM5023 controller will turn off the primary-side flyback MOSFET on a cycle-by-cycle basis. However, the primary switch can’t be turned off instantly, as there are several unavoidable delays. The first delay is caused by the LEB circuit which provides leading-edge blanking. The second delay is caused by the propagation delay between the detecting point of VCS and the actual turn off of the power MOSFET. The total delay time (tPROP) refer to Figure 14, includes the current limit comparator, the logic, the gate driver, and the power MOSFET turning off.

The propagation delay causes the peak-primary current to overshoot, the overshoot increase the maximum peak current beyond the calculated value. The peak-current overshoot increase as the AC line voltage increase because of the increase in the slope of the primary current, shown in Equation 20.

Equation 20. LM5023 qu45_nvs961.gif

This increase in the peak-input-current overshoot causes a wide variation of overpower limit in a flyback converter. In Figure 4, the overpower limit increases with the input line voltage because of IPK(max) increase shown in Equation 21 through Equation 23.

Equation 21. LM5023 qu46_nvs961.gif
Equation 22. LM5023 qu47_nvs961.gif
Equation 23. LM5023 qu48_nvs961.gif
LM5023 linecurrent_nvs961.gif Figure 14. Line-Current Feedforward

To improve the overpower limit accuracy over the full universal input line, the LM5023 integrates line current limit feedforward. Line current limit feedforward improve the overpower limit by summing a current proportional to the input rectified line into the current sense resistor (RSENSE), refer to Figure 15. The current proportional to the input line biases up the CS pin, this turns off the flyback MOSFET earlier at high input line. This feature compensates for the propagation delays creating a overpower protection that is nearly constant over the universal input line.

To implement line current limit feedforward, the first step is to calculate the QR switching frequency at low line and then at high line when the power supply is operating in current limit.

For this example:

  • Lp = 400 µH
  • RSENSE = 0.15 Ω
  • VDC(min) = 127 V
  • VDC(max) = 325 V
  • TPROP = 160 ns
  • VCS = 0.5 V
  • NAUX = 10.9
  • NPS = NP/NS = 6
  • tDLY = 580 ns
Equation 24. LM5023 qu20_nvs961.gif
Equation 25. LM5023 qu21_nvs961.gif
Equation 26. LM5023 qu22_nvs961.gif
Equation 27. LM5023 qu23_nvs961.gif

The next step is to calculate the uncompensated output power at the minimum and maximum input line voltage while in current limit.

Equation 28. LM5023 qu24_nvs961.gif
Equation 29. LM5023 qu25_nvs961.gif
Equation 30. LM5023 qu26_nvs961.gif
Equation 31. LM5023 qu27_nvs961.gif

Step three is to calculate the peak current at high line so it does not deliver more power than while it is operating at low line (94.9 W). One thing that complicates the line current limit feedforward calculation is that with quasi-resonant operation the switching frequency changes with line and load. We have two equations and two unknowns, the peak-primary current and the QR frequency.

Equation 32. LM5023 qu29_nvs961.gif
Equation 33. LM5023 qu30_nvs961.gif
Equation 34. LM5023 qu31_nvs961.gif

Step four is to calculate the peak current.

Equation 35. LM5023 qu32_nvs961.gif
Equation 36. LM5023 qu33_nvs961.gif
Equation 37. LM5023 qu34_nvs961.gif
Equation 38. LM5023 qu35_nvs961.gif

For the power supply to go into pulse-by-pulse current limit the voltage across the current sense resistor must be 0.5 V.

Equation 39. LM5023 qu36_nvs961.gif

VCS_OFFSET is the required voltage offset that must be injected across the current sense resistor, RSENSE.

Equation 40. LM5023 qu37_nvs961.gif

After calculating the required offset voltage, use Equation 41 and Equation 42 to calculate the required current feedforward.

While the main flyback switch is on, Q1, the voltage on the auxiliary winding will be negative and proportional to the rectified line.

Equation 41. LM5023 qu38_nvs961.gif
Equation 42. LM5023 qu39_nvs961.gif

IQR should be chosen in the range of 1 mA to 4 mA. The demagnetization circuit impedance should be calculated to limit the maximum current flowing through QR pin to less than 4 mA.

Equation 43. ROFFSET = 6.6 kΩ + REXTERNAL

where

  • NAUX is the number of turns on the Flyback primary (Np) divided by the number of turns on the transformer Auxiliary (NAUX) winding.

The 6.6-kΩ resistance is internal to the LM5023.

The current mirror in the QR pin input has a gain of 100; this will offset the voltage on the current sense pin shown in Equation 44.

Equation 44. LM5023 qu40_nvs961.gif

Set IQR = 1.75 mA

Equation 45. LM5023 qu41_nvs961.gif
Equation 46. LM5023 qu42_nvs961.gif
Equation 47. LM5023 qu43_nvs961.gif
Equation 48. LM5023 qu44_nvs961.gif

No external resistor is required based on the applications describe above, so a 499-Ω resistor and 100-pF capacitor are installed in the CS pin input as a noise filter.

LM5023 feedforward_nvs961.gif Figure 15. Current Feedforward

8.2.2.2.1 Overvoltage Protection

Output overvoltage protection is implemented with the LM5023 by monitoring the QR pin during the time when the main flyback MOSFET is off and the energy stored in the transformer primary is being transferred to the secondary. There is a delay prior to sampling the QR pin during the MOSFETs off time, TOVP. There are two reasons for the delay, the first is to blank the voltage spike which is a result of the transformers leakage inductance. The second is to improve the accuracy of the output voltage sensing, referring to the transformer auxiliary winding voltage shown in Figure 11. It is clear there is a down slope in the voltage which represents the decreasing VF of the output rectifier and resistance voltage drop (IS x RS) as the secondary current decreases to zero, so by delaying the sampling of the QR voltage a more accurate representation of the output voltage is achieved.

Connected to the QR pin is a comparator with a 3.0-V reference. The transformers auxiliary voltage is proportional to VOUT by the transformers turns ratio:

Equation 49. LM5023 qu49_nvs961.gif

To set the OVP, a voltage divider is connected to the transformers auxiliary winding, refer to Figure 14. In Line Current-Limit Feedforward equations were developed to improve the power limit. Resistor R1 was calculated for line current limit feedforward; to implement OVP we now need to calculate R2.

Equation 50. LM5023 qu50_nvs961.gif
Equation 51. LM5023 qu51_nvs961.gif

When an OVP fault has been detected, the LM5023 OUT driver is latched-off. VCC will discharge to VCCMIN and the VSD pin will be asserted high, allowing the depletion mode FET to turn-on and charge up the VCC capacitor to VCCON. The VSD pin will be toggled on-off-on to maintain VCC to the controller. The only way to clear the fault is to removed the input power and allow the controllers VCC voltage to drop below VRST, 5.0 V.

8.2.2.3 Valley Switching

For QR operation the flyback MOSFET is turned on with the minimum drain voltage. The delay on the auxiliary winding can be adjusted with an external resistor and capacitor to improve valley switching. The delay-time, tDLY, must equal half of the natural oscillation in Equation 52

Equation 52. LM5023 qu52_nvs961.gif

By substituting Equation 53.

Equation 53. LM5023 qu53_nvs961.gif

We can calculate the RC time constant to achieve the minimum drain voltage when the LM5023 turns on the Flyback MOSFET.

Equation 54. LM5023 qu54_nvs961.gif

The LM5023 QR pin’s capacitance is approximately 20 pF, so CdUSED = Cd –20 pF

Equation 55. LM5023 qu55_nvs961.gif

R1 and R2 were previously calculated to set the line current limit feedforward and overvoltage protection.

8.2.2.4 Hiccup Mode

Hiccup Mode is a method to prevent the power supply from over-heating during and extended overload condition. In an overload fault, the current limit comparator turns off the driver output on pulse-by-pulse basis. This starts the over load detection timer, after the over load detection timer (OLDT) times out, the current limit comparator is rechecked, if the power supply is still in an overload condition, the OUT drive is latched-off and VCC is allowed to drop to VCCOFF (7.5 V).

When VCC reaches VCCOFF, the VSD open drain output is disabled allowing the depletion mode start-up FET to turn-on, charging up the VCC capacitor to VCCON (12.5 V). When VCC reaches VCCON, the VSD output goes low turning-off the depletion mode FET. The VCC capacitor is discharged from VCCON to VCCOFF at a rate proportional to the VCC capacitor and the ICCST current (340-µA typical). The charging and discharging of the VCC capacitor is repeated four times (refer to Figure 16) use Equation 56 to figure the total Hiccup time.

Equation 56. LM5023 qu56_nvs961.gif

After allowing VCC to charge and discharge four times, the LM5023 goes through an auto restart sequence, enabling the LM5023 soft-start and driver output. It is important to set the over load detection timer long enough so that under low input-line and full-load conditions that the power supply will have enough time to start-up.

The over load detection timer can be set with the resister in series with the VSD pin VSD), refer to Figure 8.

Equation 57. LM5023 qu57_nvs961.gif
Equation 58. LM5023 qu58_nvs961.gif

Normally it is recommended that RVSD > 1 MΩ, if a lower value is used then the standby power will be higher.

Assuming the depletion mode FET charges the VCC capacitor with 2 mA, VCC capacitor is 10 µF.

Equation 59. LM5023 qu59_nvs961.gif
Equation 60. LM5023 qu60_nvs961.gif
Equation 61. LM5023 qu61_nvs961.gif
LM5023 hiccupmode_nvs961.gif Figure 16. Hiccup Mode Timing

8.2.3 Application Curves

LM5023 C001_SNVA686.png
Figure 17. LM5023 EVM Efficiency
LM5023 3.43A_Load_nva686.gif
CH1: OUT, 10 V/div CH2: SS, 2 V/div
CH3: VCC, 5 V/div CH4: VOUT, 5 V/div
Figure 19. 115-V Start-Up, 3.43-A Load
LM5023 3.43A_Load_230_nva686.gif
CH1: OUT, 10 V/div CH2: SS, 2 V/div
CH3: VCC, 5 V/div CH4: VOUT, 5 V/div
Figure 21. 230-V Start-Up, 3.43-A Load
LM5023 qr_230_nva686.gif
CH1: OUT, 10 V/div CH2: CS, 200 mV/div
CH4: VDS, 100 V/div
Figure 23. QR Waveforms VIN 230 VAC, IOUT 3.43 A
LM5023 0.1A_Load_nva686.gif
CH1: OUT, 10 V/div CH2: SS, 2 V/div
CH3: VCC, 5 V/div CH4: VOUT, 5 V/div
Figure 18. 115-V Start-Up, 0.1-A Load
LM5023 0.1A_Load_230_nva686.gif
CH1: OUT, 10 V/div CH2: SS, 2 V/div
CH3: VCC, 5 V/div CH4: VOUT, 5 V/div
Figure 20. 230-V Start-Up, 0.1-A Load
LM5023 qr_waveforms115_nva686.gif
CH1: OUT, 10 V/div CH2: CS, 200 mV/div
CH4: VDS, 100 V/div
Figure 22. QR Waveforms VIN 115 VAC, IOUT 3.43 A