SNVS565I November 2008 – August 2015 LM5085 , LM5085-Q1

PRODUCTION DATA.

- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

- NGQ|8
- DGK|8
- DGN|8

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

The LM5085/LM5085-Q1 devices are step-down DC-DC converters. The devices are typically used to convert a higher DC voltage to a lower DC voltage. Use the following design procedure to select component values. Alternately, use the WEBENCH® software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process.

The final circuit is shown in Figure 25, and its performance is presented in Figure 29 through Figure 32.

Referring to *Functional Block Diagram*, the circuit is to be configured for the following specifications:

- V
_{OUT}= 5V - V
_{IN}= 7V to 55V, 12V Nominal - Maximum load current (I
_{OUT(max)}) = 5A - Minimum load current (I
_{OUT(min)}) = 600mA (for continuous conduction mode) - Switching Frequency (F
_{SW}) = 300kHz - Maximum allowable output ripple (V
_{OS}) = 5mVp-p - Selected PFET: Vishay Si7465

The procedure for calculating the external components is illustrated with the following design example.

Selected PFET: Vishay Si7465

**R _{FB1} and R_{FB2}:** These resistors set the output voltage. The ratio of these resistors is calculated from:

Equation 15. R_{FB2}/R_{FB1} = (V_{OUT}/1.25V) - 1

For this example, R_{FB2}/R_{FB1} = 3. Typically, R_{FB1} and R_{FB2} should be chosen from standard value resistors in the range of 1kΩ to 20kΩ which satisfy the above ratio. For this example, R_{FB2} = 10kΩ, and R_{FB1} = 3.4kΩ.

**R _{T}, PFET:** Before selecting the R

Equation 16.

A standard value 90.9kΩ resistor is selected. Using Equation 3, the minimum on-time at the PGATE pin, which occurs at maximum input voltage (55V), is calculated to be 300ns. This minimum one-shot period is sufficiently longer than the minimum recommended value of 150ns. The minimum on-time at the SW node (junction of Q1, D1, L1) is longer due to the delay added by the PFET (57ns). Therefore the minimum SW node on-time is 357ns at 55V. The maximum on-time at the SW node is calculated to be 2.55µs at 7V.

**L1:** The main parameter controlled by the inductor value is the current ripple amplitude (I_{OR}). See Figure 26. The minimum load current for continuous conduction mode is used to determine the maximum allowable ripple such that the inductor current valley does not fall to zero. Continuous conduction mode operation at minimum load current is not a requirement of the LM5085, but serves as a guideline for selecting L1. For this example, the maximum ripple current is:

Equation 17. I_{OR(max)} = 2 x I_{OUT(min)} = 1.2 Amp

If the minimum load current of the application is zero, a good initial estimate for the maximum ripple current (I_{OR(max)}) is 20% of the maximum load current. The ripple calculated in Equation 17 is then used in the following equation to calculate L1:

Equation 18.

A standard value 15µH inductor is selected. Using this inductance value, the maximum ripple current amplitude, which occurs at maximum input voltage, is calculated to be 1.19 Ap-p. The peak current (I_{PK}) at maximum load current is 5.6A. However, the current rating of the selected inductor must be based on the maximum current limit value calculated below.

**R _{SEN}, R_{ADJ}:** To achieve good current limit accuracy and avoid over designing the power stage components, the sense resistor method is used for current limiting in this example. A standard value 10mΩ resistor is selected for R

Equation 19. I_{CL(min)} = 5A + 1.19A/2 = 5.6A

At this current level the voltage across R_{SEN} is 56mV. Adding the current limit comparator offset of 9mV (max) increases the required current limit threshold to 6.5A. Using Equation 9 with the minimum value for the ADJ pin current (32µA), the required R_{ADJ} resistor is calculated to be:

Equation 20.

A standard value 2.1kΩ resistor is selected. The nominal current limit threshold is:

Equation 21.

Using the tolerances for the ADJ pin current and the current limit comparator offset, the maximum current limit threshold is calculated to be:

Equation 22.

The minimum current limit threshold is:

Equation 23.

The load current in each case is equal to the current limit threshold minus half the current ripple amplitude. The recommended value of 1000pF for C_{ADJ} is used in this example.

**C _{OUT}:** Since the maximum allowed output ripple voltage is very low in this example (5 mVp-p), the minimum ripple configuration (R3, C1, and C2 in the Block Diagram) must be used. The resulting ripple at V

Equation 24.

where I_{OR(max)} is the maximum ripple current calculated above, and V_{RIPPLE} is the allowable ripple at V_{OUT}.

Equation 25.

A 100µF capacitor is selected. Typically the ripple amplitude will be higher than the calculations indicate due to the capacitor’s ESR.

**R3, C1, C2:** The minimum ripple configuration uses these three components to generate the ripple voltage required at the FB pin since there is insufficient ripple at V_{OUT}. A minimum of 25 mVp-p must be applied to the FB pin to obtain stable constant frequency operation. R3 and C1 are selected to generate a sawtooth waveform at their junction, and that waveform is AC coupled to the FB pin via C2. The values of the three components are determined using the following procedure:

Equation 26. Calculate V_{A} = V_{OUT} - (V_{SW} x (1 – (V_{OUT}/V_{IN(min)})))

where V_{SW} is the absolute value of the voltage at the SW node during the off-time, typically 0.5V to 1V depending on the diode D1. Using a typical value of 0.65V, V_{A} calculates to 4.81V. V_{A} is the nominal DC voltage at the R3/C1 junction, and is used in the next equation to calculate the R3-C3 product:

Equation 27.

where t_{ON} is the maximum on-time (at minimum input voltage), and ΔV is the desired ripple amplitude at the R3-C1 junction. For ripple voltage of 25 mVp-p:

Equation 28.

R3 and C1 are then selected from standard value components to produce the product calculated above. Typical values for C1 are 3000pF to 10,000pF, and R3 is typically from 10kΩ to 300kΩ. C2 is then chosen large compared to C1, typically 0.1µF. For this example, 3300pF is chosen for C1, requiring R3 to be 67.7kΩ. A standard value 66.5kΩ resistor is selected.

**C _{IN}, C_{BYP}:**These capacitors limit the voltage ripple at VIN by supplying most of the switch current during the on-time. At maximum load current, when Q1 is switched on, the current through Q1 suddenly increases to the lower peak of the inductor’s ripple current, then ramps up to the upper peak, and then drops to zero at turn-off. The average current during the on-time is the load current. For a worst case calculation, these capacitors must supply this average load current during the maximum on-time, while limiting the voltage drop at VIN. For this example, 0.5V is selected as the maximum allowable droop at VIN. The minimum input capacitance is calculated from:

Equation 29.

A 33µF electrolytic capacitor is selected for C_{IN}, and a 1µF ceramic capacitor is selected for C_{BYP}. Due to the ESR of C_{IN}, the ripple at VIN will likely be higher than the calculation indicates, and therefore it may be desirable to increase C_{IN} to 47µF or 68µF. C_{BYP} must be located as close as possible to the VIN and GND pins of the LM5085. The voltage rating for both capacitors must be at least 55V. The RMS ripple current rating for the input capacitors must also be considered. A good approximation for the required ripple current rating is I_{RMS} > I_{OUT}/2.

**D1:** A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed transitions at the SW node may affect the regulator’s operation due to the diode’s reverse recovery transients. The diode must be rated for the maximum input voltage, and the worst case current limit level. The average power dissipation in the diode is calculated from:

Equation 30. P_{D1} = V_{F} x I_{OUT} x (1-D)

where V_{F} is the diode’s forward voltage drop, and D is the on-time duty cycle. Using Equation 1, the minimum duty cycle occurs at maximum input voltage, and is calculated to be ≊9.1% in this example. The diode power dissipation calculates to be:

Equation 31. P_{D1} = 0.65V x 5A x (1- 0.091) = 2.95W

**C _{VCC}:** The capacitor at the VCC pin (from VIN to VCC) provides not only noise filtering and stability for the VCC regulator, but also provides the surge current for the PFET gate drive. The typical recommended value for C

**IC Power Dissipation:** The maximum power dissipated in the LM5085 package is calculated using Equation 14 at the maximum input voltage. The Total Gate Charge for the Si7465 PFET is specified to be 40nC (max) in its data sheet. Therefore the total power dissipation within the LM5085 is calculated to be:

Equation 32. P_{DISS} = 55V x ((40nC x 300kHz) + 1.4mA) = 737mW

Using an HVSSOP package with a θ_{JA} of 46°C/W produces a temperature rise of 34°C from junction to ambient.

The minimum ripple configuration employing C1, C2, and R3 in Figure 25 results in a low ripple amplitude at V_{OUT} determined mainly by the characteristics of the output capacitor and the ripple current in L1. This configuration allows multiple ceramic capacitors to be used for V_{OUT} if the output voltage is provided to several places on the PC board. However, if a slightly higher level of ripple at V_{OUT} is acceptable in the application, and distributed capacitance is not used, the ripple required for the FB comparator pin can be generated with fewer external components using the circuits shown below.

**a) Reduced ripple configuration:** In Figure 27, R3, C1 and C2 are removed (compared to Figure 25). A low value resistor (R4) is added in series with C_{OUT}, and a capacitor (Cff) is added across R_{FB2}. Ripple is generated at V_{OUT} by the inductor ripple current flowing through R4, and that ripple voltage is passed to the FB pin via Cff. The ripple at V_{OUT} can be set as low as 25 mVp-p since it is not attenuated by R_{FB2} and R_{FB1}. The minimum value for R4 is calculated from:

Equation 33.

where I_{OR(min)} is the minimum ripple current, which occurs at minimum input voltage. The minimum value for Cff is determined from:

Equation 34.

where t_{ON(max)} is the maximum on-time, which occurs at minimum VIN. The next larger standard value capacitor should be used for Cff.

**b) Lowest cost configuration:** This configuration, shown in Figure 28, is the same as Figure 27 except Cff is removed. Since the ripple voltage at V_{OUT} is attenuated by R_{FB2} and R_{FB1}, the minimum ripple required at V_{OUT} is equal to:

Equation 35. V_{RIP(min)} = 25mV x (R_{FB2} + R_{FB1})/R_{FB1}

The minimum value for R4 is calculated from:

Equation 36.

where I_{OR(min)} is the minimum ripple current, which occurs at minimum input voltage.