SNVS349E February   2005  – August 2016 LM5105

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Dissipation Considerations
    2. 9.2 HS Transient Voltages Below Ground
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DPR Package
10-Pin WSON
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 VDD P Positive gate drive supply. Decouple VDD to VSS using a low ESR/ESL capacitor, placed as close to the IC as possible.
2 HB P High-side gate driver bootstrap rail. Connect the positive terminal of bootstrap capacitor to the HB pin and connect negative terminal to HS. The Bootstrap capacitor must be placed as close to IC as possible.
3 HO O High-side gate driver output. Connect to the gate of high side N-MOS device through a short, low inductance path.
4 HS P High-side MOSFET source connection. Connect to the negative terminal of the bootstrap capacitor and to the source of the high side N-MOS device.
5 NC — Not connected.
6 RDT I Dead-time programming pin. A resistor from RDT to VSS programs the turnon delay of both the high and low side MOSFETs. The resistor must be placed close to the IC to minimize noise coupling from adjacent PCB traces.
7 EN I Logic input for driver disable or enable. TTL compatible threshold with hysteresis. LO and HO are held in the low state when EN is low.
8 IN I Logic input for gate driver. TTL compatible threshold with hysteresis. The high side MOSFET is turned on and the low side MOSFET turned off when IN is high.
9 VSS G Ground return. All signals are referenced to this ground.
10 LO O Low-side gate driver output. Connect to the gate of the low side N-MOS device with a short, low inductance path.
— Exposed Pad — It is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PCB to aid thermal dissipation.
(1) G = Ground, I = Input, O = Output, P = Power