SNVS300H July   2004  – September 2016 LM5111

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout
      2. 8.3.2 Output Stage
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VCC
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bias Supply Voltage
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Drive Power Requirement Calculations in LM5111
      2. 11.3.2 Continuous Current Rating of LM5111
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Attention must be given to board layout when using LM5111. Some important considerations include:

  • A Low ESR/ESL capacitor must be connected close to the IC and between the VCC and VEE pins to support high peak currents being drawn from VCC during turnon of the MOSFET.
  • Proper grounding is crucial. The drivers need a very low impedance path for current return to ground avoiding inductive loops. The two paths for returning current to ground are a) between LM5111 VEE pin and the ground of the circuit that controls the driver inputs, b) between LM5111 VEE pin and the source of the power MOSFET being driven. All these paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance. All these ground paths should be kept distinctly separate to avoid coupling between the high current output paths and the logic signals that drive the LM5111. A good method is to dedicate one copper plane in a multi-layered PCB to provide a common ground surface.
  • With the rise and fall times in the range of 10 ns to 30 ns, care is required to minimize the lengths of current carrying conductors to reduce their inductance and EMI from the high di/dt transients generated by the LM5111.
  • The LM5111 footprint is compatible with other industry standard drivers including the TC4426/27/28 and UCC27323/4/5.
  • If either channel is not being used, the respective input pin (IN_A or IN_B) should be connected to either VEE or VCC to avoid spurious output signals.

11.2 Layout Example

LM5111 layout.gif Figure 15. Layout

11.3 Thermal Considerations

The primary goal of thermal management is to maintain the integrated circuit (IC) junction temperature (TJ) below a specified maximum operating temperature to ensure reliability. It is essential to estimate the maximum TJ of IC components in worst case operating conditions. The junction temperature is estimated based on the power dissipated in the IC and the junction to ambient thermal resistance θJA for the IC package in the application board and environment. The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment.

11.3.1 Drive Power Requirement Calculations in LM5111

The LM5111 dual low side MOSFET driver is capable of sourcing/sinking 3A/5A peak currents for short intervals to drive a MOSFET without exceeding package power dissipation limits. High peak currents are required to switch the MOSFET gate very quickly for operation at high frequencies.

LM5111 20112307.gif Figure 16. Driver Output Stage and Load

The schematic above shows a conceptual diagram of the LM5111 output and MOSFET load. Q1 and Q2 are the switches within the gate driver. RG is the gate resistance of the external MOSFET, and CIN is the equivalent gate capacitance of the MOSFET. The gate resistance Rg is usually very small and losses in it can be neglected. The equivalent gate capacitance is a difficult parameter to measure since it is the combination of CGS (gate to source capacitance) and CGD (gate to drain capacitance). Both of these MOSFET capacitances are not constants and vary with the gate and drain voltage. The better way of quantifying gate capacitance is the total gate charge QG in coulombs. QG combines the charge required by CGS and CGD for a given gate drive voltage VGATE.

Assuming negligible gate resistance, the total power dissipated in the MOSFET driver due to gate charge is approximated by

Equation 2. PDRIVER = VGATE × QG × FSW

where

  • FSW = switching frequency of the MOSFET

For example, consider the MOSFET MTD6N15 whose gate charge specified as 30 nC for VGATE = 12 V.

The power dissipation in the driver due to charging and discharging of MOSFET gate capacitances at switching frequency of 300 kHz and VGATE of 12 V is equal to

Equation 3. PDRIVER = 12 V × 30 nC × 300 kHz = 0.108 W.

If both channels of the LM5111 are operating at equal frequency with equivalent loads, the total losses will be twice as this value which is 0.216 W.

In addition to the above gate charge power dissipation, transient power is dissipated in the driver during output transitions. When either output of the LM5111 changes state, current will flow from VCC to VEE for a very brief interval of time through the output totem-pole N and P channel MOSFETs. The final component of power dissipation in the driver is the power associated with the quiescent bias current consumed by the driver input stage and Under-voltage lockout sections.

Characterization of the LM5111 provides accurate estimates of the transient and quiescent power dissipation components. At 300-kHz switching frequency and 30-nC load used in the example, the transient power will be 8 mW. The 1-mA nominal quiescent current and 12-V VGATE supply produce a 12-mW typical quiescent power.

Therefore the total power dissipation

Equation 4. PD = 0.216 + 0.008 + 0.012 = 0.236 W.

We know that the junction temperature is given by

Equation 5. TJ = PD × θJA + TA

Or the rise in temperature is given by

Equation 6. TRISE = TJ − TA = PD × θJA

For SOIC package, θJA is estimated as 170°C/W for the conditions of natural convection. For MSOP-PowerPAD, θJA is typically 60°C/W.

Therefore for SOIC TRISE is equal to

Equation 7. TRISE = 0.236 × 170 = 40.1°C

11.3.2 Continuous Current Rating of LM5111

The LM5111 can deliver pulsed source/sink currents of 3 A and 5 A to capacitive loads. In applications requiring continuous load current (resistive or inductive loads), package power dissipation, limits the LM5111 current capability far below the 5-A sink and 3-A source capability. Rated continuous current can be estimated both when sourcing current to or sinking current from the load. For example when sinking, the maximum sink current can be calculated as:

Equation 8. LM5111 20112308.gif

where

  • RDS(on) is the on resistance of lower MOSFET in the output stage of LM5111

Consider TJ(max) of 125°C and θJA of 170°C/W for an SO-8 package under the condition of natural convection and no air flow. If the ambient temperature (TA) is 60°C, and the RDS(on) of the LM5111 output at TJ(max) is 2.5 Ω, this equation yields ISINK(max) of 391 mA which is much smaller than 5-A peak pulsed currents.

Similarly, the maximum continuous source current can be calculated as

Equation 9. LM5111 20112309.gif

where

  • VDIODE is the voltage drop across hybrid output stage which varies over temperature and can be assumed to be about 1.1 V at TJ(max) of 125°C

Assuming the same parameters as above, this equation yields ISOURCE(max) of 347 mA.