SNVSAW9 June   2017 LM5122-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM5122-Q1
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Lockout (UVLO)
      2. 7.3.2  High Voltage VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  Slope Compensation
      5. 7.3.5  Error Amplifier
      6. 7.3.6  PWM Comparator
      7. 7.3.7  Soft-Start
      8. 7.3.8  HO and LO Drivers
      9. 7.3.9  Bypass Operation (VOUT = VIN)
      10. 7.3.10 Cycle-by-Cycle Current Limit
      11. 7.3.11 Clock Synchronization
      12. 7.3.12 Maximum Duty Cycle
      13. 7.3.13 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Control (Forced-PWM Mode and Diode-Emulation Mode)
      2. 7.4.2 MODE Control (Skip-Cycle Mode and Pulse-Skipping Mode)
      3. 7.4.3 Hiccup-Mode Overload Protection
      4. 7.4.4 Slave Mode and SYNCOUT
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Feedback Compensation
      2. 8.1.2 Sub-Harmonic Oscillation
      3. 8.1.3 Interleaved Boost Configuration
      4. 8.1.4 DCR Sensing
      5. 8.1.5 Output Overvoltage Protection
      6. 8.1.6 SEPIC Converter Simplified Schematic
      7. 8.1.7 Non-Isolated Synchronous Flyback Converter Simplified Schematic
      8. 8.1.8 Negative to Positive Conversion
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Custom Design With WEBENCH® Tools
        2.  Timing Resistor RT
        3.  UVLO Divider RUV2, RUV1
        4.  Input Inductor LIN
        5.  Current Sense Resistor RS
        6.  Current Sense Filter RCSFP, RCSFN, CCS
        7.  Slope Compensation Resistor RSLOPE
        8.  Output Capacitor COUT
        9.  Input Capacitor CIN
        10. VIN Filter RVIN, CVIN
        11. Bootstrap Capacitor CBST and Boost Diode DBST
        12. VCC Capacitor CVCC
        13. Output Voltage Divider RFB1, RFB2
        14. Soft-Start Capacitor CSS
        15. Restart Capacitor CRES
        16. Low-Side Power Switch QL
        17. High-Side Power Switch QH and Additional Parallel Schottky Diode
        18. Snubber Components
        19. Loop Compensation Components CCOMP, RCOMP, CHF
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The LM5122 device is a step-up dc-dc converter. The device is typically used to convert a lower dc voltage to a higher dc voltage. Use the following design procedure to select component values for the LM5122 device. Alternately, use the WEBENCH® software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process.

Feedback Compensation

The open loop response of a boost regulator is defined as the product of modulator transfer function and feedback transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback gain. The modulator transfer function of a current mode boost regulator including a power stage transfer function with an embedded current loop can be simplified as one pole, one zero, and one right-half-plane (RHP) zero system.

Modulator transfer function is defined as follows:

Equation 16. LM5122-Q1 eq18_nvs954.gif


  • LM5122-Q1 eq19_nvs954.gif
  • LM5122-Q1 eq20_nvs954.gif
  • LM5122-Q1 eq21_nvs954.gif
  • LM5122-Q1 eq22_nvs954.gif
  • LM5122-Q1 eq23_nvs954.gif
  • n is the number of the phase.

If the equivalent series resistance (ESR) of COUT (RESR) is small enough and the RHP zero frequency is far away from the target crossover frequency, the modulator transfer function can be further simplified to one pole system and the voltage loop can be closed with only two loop compensation components, RCOMP and CCOMP, leaving a single pole response at the crossover frequency. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin.

The feedback transfer function includes the feedback resistor divider and loop compensation of the error amplifier. RCOMP, CCOMP, and optional CHF configure the error amplifier gain and phase characteristics, create a pole at origin, a low frequency zero and a high frequency pole.

Feedback transfer function is defined as follows:

Equation 17. LM5122-Q1 eq25_nvs954.gif


  • LM5122-Q1 eq26_nvs954.gif
  • LM5122-Q1 eq27_nvs954.gif
  • LM5122-Q1 eq28_nvs954.gif

The pole at the origin minimizes the output steady state error. Place the low frequency zero to cancel the load pole of the modulator. The high frequency pole can be used to cancel the zero created by the output capacitor ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an order of magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at the crossover frequency. The high frequency pole should be placed beyond the crossover frequency since the addition of CHF adds a pole in the feedback transfer function.

The crossover frequency (open loop bandwidth) is usually selected between one twentieth and one fifth of the fSW. In a simplified formula, the estimated crossover frequency can be defined as:

Equation 18. LM5122-Q1 eq29_nvs954.gif


  • LM5122-Q1 eq9_nvs954.gif

For higher crossover frequency, RCOMP can be increased, while proportionally decreasing CCOMP. Conversely, decreasing RCOMP while proportionally increasing CCOMP, results in lower bandwidth while keeping the same zero frequency in the feedback transfer function.

The modulator transfer function can be measured by a network analyzer and the feedback transfer function can be configured for the desired open loop transfer function. If the network analyzer is not available, step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot/undershoot with a damped response.

Sub-Harmonic Oscillation

Peak current mode regulator can exhibit unstable behavior when operating above 50% duty cycle. This behavior is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the SW pin. Sub-harmonic oscillation can be prevented by adding an additional slope voltage ramp (slope compensation) on top of the sensed inductor current. By choosing K ≥ 0.82~1, the sub-harmonic oscillation is eliminated even with wide varying input voltage.

In time-domain analysis, the steady-state inductor current starting from an initial point returns to the same point. When the amplitude of an end cycle current error (dI1) caused by an initial perturbation (dI0) is less than the amplitude of dI0 or dI1/dI0 > –1, the perturbation naturally disappears after a few cycles. When dl1/dl0 < –1, the initial perturbation no longer disappear, it results in sub-harmonic oscillation in steady-state.

LM5122-Q1 Effect of Initial Pert.gif Figure 27. Effect of Initial Perturbation when dl1/dl0 < -1

dI1/dI0 can be calculated as:

Equation 19. LM5122-Q1 eq31_nvs954.gif

The relationship between dI1/dI0 and K factor is illustrated graphically in Figure 28.

LM5122-Q1 dl1 dl0 vs K.gif Figure 28. dl1/dl0 vs K Factor

The absolute minimum value of K is 0.5. When K < 0.5, the amplitude of dl1 is greater than the amplitude of dl0 and any initial perturbation results in sub-harmonic oscillation. If K = 1, any initial perturbation is removed in one switching cycle. This is known as one-cycle damping. When –1 < dl1/dl0 < 0, any initial perturbationis under-damped. Any perturbation is over-damped when 0 < dl1/dl0 < 1.

In the frequency-domain, Q, the quality factor of sampling gain term in modulator transfer function, is used to predict the tendency for sub-harmonic oscillation, which is defined as:

Equation 20. LM5122-Q1 eq32_nvs954.gif

The relationship between Q and K factor is shown in Figure 29.

LM5122-Q1 Sampling Gain Q vs K.gif Figure 29. Sampling Gain Q vs K Factor

The recommended absolute minimum value of K is 0.5. High gain peaking when K is less than 0.5 results sub-harmonic oscillation at fSW/2. A higher value of K factor may introduce additional phase shift near the crossover frequency, but has the benefit of reducing noise susceptibility in current loop. The maximum allowable value of K factor can be calculated by the maximum crossover frequency equation in frequency analysis formulas in Table 2.

Table 2. Boost Regulator Frequency Analysis

LM5122-Q1 eq105_nvs954.gif
LM5122-Q1 eq37_nvs954.gif
Modulator DC gain (2)
LM5122-Q1 eq34_nvs954.gif
RHP zero (2)
LM5122-Q1 eq35_nvs954.gif
ESR zero
LM5122-Q1 eq36_nvs954.gif
LM5122-Q1 eq38_nvs954.gif
ESR pole Not considered
LM5122-Q1 eq39_nvs954.gif
Dominant load pole
LM5122-Q1 eq40_nvs954.gif
Sampled gain inductor pole Not considered
LM5122-Q1 eq41_nvs954.gif
LM5122-Q1 eq42_nvs954.gif
Quality factor Not considered
LM5122-Q1 eq43_nvs954.gif
Sub-harmonic double pole Not considered
LM5122-Q1 eq44_nvs954.gif


LM5122-Q1 eq45_nvs954.gif
K factor K = 1
LM5122-Q1 eq47_nvs954.gif
LM5122-Q1 eq48_nvs954.gif
Feedback DC gain
LM5122-Q1 eq49_nvs954.gif
Mid-band Gain
LM5122-Q1 eq50_nvs954.gif
Low frequency zero
LM5122-Q1 eq51_nvs954.gif
High frequency pole
LM5122-Q1 eq52_nvs954.gif
LM5122-Q1 eq96_nvs954.gif
LM5122-Q1 eq54_nvs954.gif
LM5122-Q1 eq55_nvs954.gif
Crossover frequency (3)
(Open loop band width)
LM5122-Q1 eq56_nvs954.gif
Use graphic tool
Maximum cross over frequency(4)
LM5122-Q1 eq57_nvs954.gif
LM5122-Q1 eq58_nvs954.gif
LM5122-Q1 eq59_nvs954.gif
, whichever is smaller
Comprehensive equation includes an inductor pole and a gain peaking at fSW / 2, which is caused by sampling effect of the current mode control. Also, it assumes that a ceramic capacitor COUT2 (No ESR) is connected in parallel with COUT1. RESR1 represents ESR of COUT1.
With multiphase configuration, LM5122-Q1 eq60_nvs954.gif, LM5122-Q1 eq61_nvs954.gif, LM5122-Q1 eq62_nvs954.gif, and COUT = COUT of each phase x n, where n = number of phases. As is the current sense amplifier gain.
Assuming LM5122-Q1 eq64_nvs954.gif, LM5122-Q1 eq65_nvs954.gif, LM5122-Q1 eq66_nvs954.gif, LM5122-Q1 eq67_nvs954.gif, and LM5122-Q1 eq68_nvs954.gif.
The frequency at which 45° phase shift occurs in modulator phase characteristics.

Interleaved Boost Configuration

Interleaved operation offers many advantages in single output, high current applications such as higher efficiency, lower component stresses and reduced input and output ripple. For dual phase interleaved operation, the output power path is split reducing the input current in each phase by one-half. Ripple currents in the input and output capacitors are reduced significantly since each channel operates 180 degrees out of phase from the other. Shown in Figure 30 is a normalized (IRMS/IOUT) output capacitor ripple current vs duty cycle for both a single phase and dual phase boost converter, where IRMS is the output current ripple RMS.

LM5122-Q1 Norm Output Capac.png Figure 30. Normalized Output Capacitor RMS Ripple Current

To configure for dual phase interleaved operation, configure one device as a master and configure the other device in slave mode by connecting FB to VCC. Also connect COMP, UVLO, RES, SS and SYNCOUT on the master side to COMP, UVLO, RES, SS and SYNCIN on slave side, respectively. The compensation network is connected between master FB and the common COMP connection. The output capacitors of the two power stages are connected together at the common output.

LM5122-Q1 Dual Phased Intrlvd.gif Figure 31. Dual Phase Interleaved Boost Configuration

Shown in Figure 32 is a dual phase timing diagram. The 180° phase shift is realized by connecting SYNCOUT on the master side to the SYNCIN on the slave side.

LM5122-Q1 Dual Phase Config Tim.gif Figure 32. Dual Phase Configuration and Timing Diagram

Each channel is synchronized by an individual external clock in Figure 33. The SYNCOUT pin is used in Figure 34 requiring only one external clock source. A 50% duty cycle of external synchronization pulse should be always provided with this daisy chain configuration.

Current sharing between phases is achieved by sharing one error amplifier output of the master controller with the 3 slave controllers. Resistor sensing is a preferred method of current sensing to accurately balance the phase currents.

LM5122-Q1 4 Phase Timing Diag [a].gif Figure 33. 4-Phase Timing Diagram Individual Clock
LM5122-Q1 4 Phase Timing Diag [b].gif Figure 34. 4-Phase Timing Diagram Daisy Chain

DCR Sensing

For the applications requiring lowest cost with minimum conduction loss, inductor DC resistance (DCR) is used to sense the inductor current rather than using a sense resistor. Shown in Figure 35 is a DCR sensing configuration using two DCR sensing resistors and one capacitor.

LM5122-Q1 DCR_sensing1.gif Figure 35. DCR Sensing

RCSN and CDCR selection must meet Equation 21 because this indirect current sensing method requires a time constant matching. CDCR is usually selected to be in the range of 0.1 µF to 2.2 µF.

Equation 21. LM5122-Q1 eq69_nvs954.gif

Smaller value of RCSN minimizes the voltage drop caused by CSN bias current, but increases the dynamic power dissipation of RCSN. The DC voltage drop of RCSN can be compensated by selecting the same value of RCSP, but the gain of current amplifier, which is typically 10, is affected by adding RCSP. The gain of current amplifier with the DCR sensing network can be determined as:

Equation 22. LM5122-Q1 eq99_nvs954.gif

Due to the reduced accuracy of DCR sensing, TI recommends FPWM operation when DCR sensing is used.

Output Overvoltage Protection

Output overvoltage protection can be achieved by adding a simple external circuit. The output overvoltage protection circuit shown in Figure 36 shuts down the LM5122 when the output voltage exceeds the overvoltage threshold set by the zener diode.

LM5122-Q1 Output Overv Prot.gif Figure 36. Output Overvoltage Protection

SEPIC Converter Simplified Schematic

LM5122-Q1 Sepic Conv Schematic.gif Figure 37. Sepic Converter Simplified Schematic

Non-Isolated Synchronous Flyback Converter Simplified Schematic

LM5122-Q1 Non Isol Synch Flyb.gif Figure 38. Non-Isolated Synchronous Flyback Converter Simplified Schematic

Negative to Positive Conversion

LM5122-Q1 simplified_schematic_negative_to_positive_converter_snvs954.gif Figure 39. Negative to Positive Converter Simplified Schematic

Typical Application

LM5122-Q1 Schematic.png Figure 40. Single Phase Example Schematic

Design Requirements

Output voltage (VOUT) 24 V
Full load current (IOUT) 4.5 A
Output Power 108 W
Minimum input voltage (VIN(MIN)) 9 V
Typical input voltage (VIN(TYP)) 12 V
Maximum input voltage (VIN(MAX)) 20 V
Switching frequency (fSW) 250 kHz

Detailed Design Procedure

Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5122 device with the WEBENCH® Power Designer.

  1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
  2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
  3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

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Timing Resistor RT

Generally, higher frequency applications are smaller but have higher losses. Operation at 250 kHz is selected for this example as a reasonable compromise between small size and high-efficiency. The value of RT for 250 kHz switching frequency is calculated as follows:

Equation 23. LM5122-Q1 eq70_nvs954.gif

A standard value of 36.5 kΩ is chosen for RT.

UVLO Divider RUV2, RUV1

The desired startup voltage and the hysteresis are set by the voltage divider RUV2, RUV1. The UVLO shutdown voltage should be high enough to enhance the low-side N-channel MOSFET switch fully. For this design, the startup voltage is set to 8.7 V which is 0.3 V below VIN(MIN). VHYS is set to 0.5 V. This results 8.2 V of VIN(SHUTDOWN). The values of RUV2, RUV1 are calculated as follows:

Equation 24. LM5122-Q1 eq71_nvs954.gif
Equation 25. LM5122-Q1 eq72_nvs954.gif

A standard value of 49.9 kΩ is selected for RUV2. RUV1 is selected to be a standard value of 8.06 kΩ.

Input Inductor LIN

The inductor ripple current is typically set between 20% and 40% of the full load current, known as a good compromise between core loss and copper loss of the inductor. Higher ripple current allows for a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. For this example, a ripple ratio (RR) of 0.25, 25% of the input current was chosen. Knowing the switching frequency and the typical output voltage, the inductor value can be calculated as follows:

Equation 26. LM5122-Q1 eq73_nvs954.gif

The closest standard value of 10 μH was chosen for LIN.

The saturation current rating of inductor should be greater than the peak inductor current, which is calculated at the minimum input voltage and full load. 8.7 V startup voltage is used conservatively.

Equation 27. LM5122-Q1 eq74_nvs954.gif

Current Sense Resistor RS

The maximum peak input current capability should be 20~50% higher than the required peak current at low input voltage and full load, accounting for tolerances. For this example, 40% is margin is chosen.

Equation 28. LM5122-Q1 eq75_nvs954.gif

A closest standard value of 4 mΩ is selected for RS. The maximum power loss of RS is calculated as follows.

Equation 29. LM5122-Q1 eq100_nvs954.gif

Current Sense Filter RCSFP, RCSFN, CCS

The current sense filter is optional. 100 pF of CCS and 100 Ω of RCSFP, RCSFN are normal recommendations. Because CSP and CSN pins are high impedance, CCS should be placed physically as close to the device.

LM5122-Q1 Curr Sense Filter.gif Figure 41. Current Sense Filter

Slope Compensation Resistor RSLOPE

The K value is selected to be 1 at the minimum input voltage. RSLOPE should be carefully selected so that the sum of sensed inductor current and slope compensation is less than COMP output high voltage.

Equation 30. LM5122-Q1 eq76_nvs954.gif
Equation 31. LM5122-Q1 eq77_nvs954.gif

A closest standard value of 100 kΩ is selected for RSLOPE.

Output Capacitor COUT

The output capacitors smooth the output voltage ripple and provide a source of charge during transient loading conditions. Also the output capacitors reduce the output voltage overshoot when the load is disconnected suddenly.

Ripple current rating of output capacitor should be carefully selected. In boost regulator, the output is supplied by discontinuous current and the ripple current requirement is usually high. In practice, the ripple current requirement can be dramatically reduced by placing high-quality ceramic capacitors earlier than the bulk aluminum capacitors close to the power switches.

The output voltage ripple is dominated by ESR of the output capacitors. Paralleling output capacitor is a good choice to minimize effective ESR and split the output ripple current into capacitors.

In this example, three 330 µF aluminum capacitors are used to share the output ripple current and source the required charge. The maximum output ripple current can be simply calculated at the minimum input voltage as follows:

Equation 32. LM5122-Q1 eq78_nvs954.gif

Assuming 60 mΩ of ESR per an output capacitor, the output voltage ripple at the minimum input voltage is calculated as follows:

Equation 33. LM5122-Q1 eq79_nvs954.gif

In practice, four 10-µF ceramic capacitors are additionally placed earlier than the bulk aluminum capacitors to reduce the output voltage ripple and split the output ripple current.

Due to the inherent path from input to output, unlimited inrush current can flow when the input voltage rises quickly and charges the output capacitor. The slew rate of input voltage rising should be controlled by a hot-swap or by starting the input power supply softly for the inrush current not to damage the inductor, sense resistor or high-side N-channel MOSFET switch.

Input Capacitor CIN

The input capacitors smooth the input voltage ripple. Assuming high-quality ceramic capacitors are used for the input capacitors, the maximum input voltage ripple which happens when the input voltage is half of the output voltage can be calculated as follows:

Equation 34. LM5122-Q1 eq80_nvs954.gif

The value of input capacitor is also a function of source impedance, the impedance of source power supply. The more input capacitor will be required to prevent a chatter condition upon power up if the impedance of source power supply is not enough low.


An R-C filter (RVIN, CVIN) on VIN pin is optional. It is not required if CIN capacitors are high-quality ceramic capacitors and placed physically close to the device. The filter helps to prevent faults caused by high frequency switching noise injection into the VIN pin. A 0.47 μF ceramic capacitor is used this example. 3 Ω of RVIN and 0.47 µF of CVIN are normal recommendations. A larger filter with 2.2 µ~4.7 µF CVIN is recommended when the input voltage is lower than 8 V or the required duty cycle is close to the maximum duty cycle limit.

LM5122-Q1 Vin Filter.gif Figure 42. VIN Filter

Bootstrap Capacitor CBST and Boost Diode DBST

The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side N-channel MOSFET device gate during each cycle’s turn-on and also supplies recovery charge for the bootstrap diode. These current peaks can be several amperes. The recommended value of the bootstrap capacitor is 0.1 μF. CBST must be a good-quality, low-ESR, ceramic capacitor located at the pins of the device to minimize potentially damaging voltage transients caused by trace inductance. The minimum value for the bootstrap capacitor is calculated as follows:

Equation 35. LM5122-Q1 eq81_nvs954.gif


  • QG is the high-side N-channel MOSFET gate charge
  • ΔVBST is the tolerable voltage droop on CBST, which is typically less than 5% of VCC or 0.15 V, conservatively

In this example, the value of the BST capacitor (CBST) is 0.1 µF.

The voltage rating of DBST must be greater than the peak SW node voltage plus 16 V. A low leakage diode is mandatory for the bypass operation. The leakage current of DBST must be low enough for the BST charge pump to maintain a sufficient high-side driver supply voltage at high temperature. A low leakage diode also prevents the possibility of excessive VCC voltage during shutdown, in high output voltage applications. If the leakage is excessive, a zener VCC clamp or bleed resistor may be required. High-side driver supply voltage must be greater than the high-side N-channel MOSFET switch’s gate plateau at the minimum input voltage.

VCC Capacitor CVCC

The primary purpose of the VCC capacitor is to supply the peak transient currents of the LO driver and bootstrap diode as well as provide stability for the VCC regulator. These peak currents can be several amperes. The value of CVCC must be at least 10 times greater than the value of CBST and should be a good-quality, low-ESR, ceramic capacitor. Place CVCC close to the pins of the device to minimize potentially damaging voltage transients caused by trace inductance. A value of 4.7 µF was selected for this design example.

Output Voltage Divider RFB1, RFB2

RFB1 and RFB2 set the output voltage level. The ratio of these resistors is calculated as follows:

Equation 36. LM5122-Q1 eq82_nvs954.gif

The ratio between RCOMP and RFB2 determines the mid-band gain, AFB_MID. A larger value for RFB2 may require a corresponding larger value for RCOMP. RFB2 should be large enough to keep the total divider power dissipation small. 49.9 kΩ in series with 825 Ω was chosen for high-side feedback resistors in this example, which results in a RFB1 value of 2.67 kΩ for 24-V output.

Soft-Start Capacitor CSS

The soft-start time (tSS) is the time for the output voltage to reach the target voltage from the input voltage. The soft-start time is not only proportional with the soft-start capacitor, but also depends on the input voltage. With 0.1 µF of CSS, the soft-start time is calculated as follows:

Equation 37. LM5122-Q1 eq83_nvs954.gif
Equation 38. LM5122-Q1 eq84_nvs954.gif

Restart Capacitor CRES

The restart capacitor determines restart delay time tRD and hiccup mode off time tRES (see Figure 26). tRD must be greater than tSS(MAX). The minimum required value of CRES can be calculated at the low input voltage as follows:

Equation 39. LM5122-Q1 eq85_nvs954.gif

A standard value of 0.47 µF is selected for CRES.

Low-Side Power Switch QL

Selection of the power N-channel MOSFET devices by breaking down the losses is one way to compare the relative efficiencies of different devices. Losses in the low-side N-channel MOSFET device can be separated into conduction loss and switching loss.

Low-side conduction loss is approximately calculated as follows:

Equation 40. LM5122-Q1 eq86_nvs954.gif

Where, D is the duty cycle and the factor of 1.3 accounts for the increase in the N-channel MOSFET device on-resistance due to heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature on-resistance of the N-channel MOSFET device can be estimated using the RDS(ON) vs temperature curves in the N-channel MOSFET datasheet.

Switching loss occurs during the brief transition period as the low-side N-channel MOSFET device turns on and off. During the transition period both current and voltage are present in the channel of the N-channel MOSFET device. The low-side switching loss is approximately calculated as follows:

Equation 41. LM5122-Q1 eq101_nvs954.gif

tR and tF are the rise and fall times of the low-side N-channel MOSFET device. The rise and fall times are usually mentioned in the N-channel MOSFET data sheet or can be empirically observed with an oscilloscope.

An additional Schottky diode can be placed in parallel with the low-side N-channel MOSFET switch, with short connections to the source and drain in order to minimize negative voltage spikes at the SW node.

High-Side Power Switch QH and Additional Parallel Schottky Diode

Losses in the high-side N-channel MOSFET device can be separated into conduction loss, dead-time loss, and reverse recovery loss. Switching loss is calculated for the low-side N-channel MOSFET device only. Switching loss in the high-side N-channel MOSFET device is negligible because the body diode of the high-side N-channel MOSFET device turns on before and after the high-side N-channel MOSFET device switches.

High-side conduction loss is approximately calculated as follows:

Equation 42. LM5122-Q1 eq87_nvs954.gif

Dead-time loss is approximately calculated as follows:

Equation 43. LM5122-Q1 eq104_nvs954.gif


  • VD is the forward voltage drop of the high-side NMOS body diode.

Reverse recovery characteristics of the high-side N-channel MOSFET switch strongly affect efficiency, especially when the output voltage is high. Small reverse recovery charge helps to increase the efficiency while also minimizes switching noise.

Reverse recovery loss is approximately calculated as follows:

Equation 44. LM5122-Q1 eq102_nvs954.gif
Equation 45.


  • QRR is the reverse recovery charge of the high-side N-channel MOSFET body diode.

An additional Schottky diode can be placed in parallel with the high-side switch to improve efficiency. Usually, the power rating of this parallel Schottky diode can be less than the high-side switch’s because the diode conducts only during dead-times. The power rating of the parallel diode should be equivalent or higher than high-side switch’s if bypass operation is required, hiccup mode operation is required or any load exists before switching.

Snubber Components

A resistor-capacitor snubber network across the high-side N-channel MOSFET device reduces ringing and spikes at the switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to the output voltage. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and 50 Ω. Increasing the value of the snubber capacitor results more damping, but this also results higher snubber losses. Select a minimum value for the snubber capacitor that provides adequate damping of the spikes on the switch waveform at heavy load. A snubber may not be necessary with an optimized layout.

Loop Compensation Components CCOMP, RCOMP, CHF

RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to produce a stable voltage loop. For a quick start, follow the following 4 steps:

  1. Select fCROSS
  2. Select the cross over frequency (fCROSS) at one fourth of the RHP zero or one tenth of the switching frequency whichever is lower.

    Equation 46. LM5122-Q1 eq88_nvs954.gif
    Equation 47. LM5122-Q1 eq89_nvs954.gif

    5.3 kHz of the crossover frequency is selected between two. RHP zero at minimum input voltage should be considered if the input voltage range is wide.

  3. Determine required RCOMP
  4. Knowing fCROSS, RCOMP is calculated as follows:

    Equation 48. LM5122-Q1 eq92_nvs954.gif

    A standard value of 68.1 kΩ is selected for RCOMP

  5. Determine CCOMP to cancel load pole. Place error amplifier zero at the twice of load pole frequency. Knowing RCOMP, CCOMP is calculated as follows:
  6. Equation 49. LM5122-Q1 eq95_nvs954.gif

    A standard value of 22 nF is selected for CCOMP

  7. Determine CHF to cancel ESR zero.
  8. Knowing RCOMP, RESR and CCOMP, CHF is calculated as follows:

    Equation 50. LM5122-Q1 eq90_nvs954.gif

    A standard value of 330 pF is selected for CHF.

Application Curves

LM5122-Q1 appc1_snvs954.gif
FSYNC = 500 kHz
Figure 43. Clock Synchronization
LM5122-Q1 appc3_snvs954.gif
Figure 45. Pulse Skip
LM5122-Q1 appc5_snvs954.gif
Figure 47. Loop Response
LM5122-Q1 appc2_snvs954.gif
Figure 44. Forced PWM
LM5122-Q1 appc4_snvs954.gif
Figure 46. Skip Cycle
LM5122-Q1 appc6_snvs954.gif
C1: VSUPPLY, C2: Inductor current VSUPPLY = 12 V
C3: VOUT, C4: SS ILOAD = 0 A
Figure 48. Start-Up