SNAS548D February 2000 – January 2015 LM555
Standard PCB rules apply to routing the LM555. The 0.1-µF capacitor in parallel with a 1-µF electrolytic capacitor should be as close as possible to the LM555. The capacitor used for the time delay should also be placed as close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity and signal integrity.
Figure 20 is the basic layout for various applications.