SNVSCH2A September   2024  – May 2025 LM65625-Q1 , LM65635-Q1 , LM65645-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Selection
      2. 7.3.2 EN Pin and Use as VIN UVLO
      3. 7.3.3 Mode Selection
        1. 7.3.3.1 MODE/SYNC Pin Uses for Synchronization
        2. 7.3.3.2 Clock Locking
      4. 7.3.4 Adjustable Switching Frequency
      5. 7.3.5 Dual Random Spread Spectrum (DRSS)
      6. 7.3.6 Internal LDO, VCC UVLO, and BIAS Input
      7. 7.3.7 Bootstrap Voltage (BST Pin)
      8. 7.3.8 Soft Start and Recovery From Dropout
      9. 7.3.9 Safety Features
        1. 7.3.9.1 Power-Good Monitor
        2. 7.3.9.2 Overcurrent and Short-Circuit Protection
        3. 7.3.9.3 Hiccup
        4. 7.3.9.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Peak Current Mode Operation
        2. 7.4.2.2 Auto Mode Operation
          1. 7.4.2.2.1 Diode Emulation
        3. 7.4.2.3 FPWM Mode Operation
        4. 7.4.2.4 Dropout
        5. 7.4.2.5 Recovery from Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Choosing the Switching Frequency
        3. 8.2.2.3 FB for Adjustable or Fixed Output Voltage Mode
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Input Capacitor Selection
        7. 8.2.2.7 CBOOT
        8. 8.2.2.8 External UVLO
        9. 8.2.2.9 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 13.5V, VEN = VIN, VOUT = 3.3V, fSW = 2.2MHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY (VIN PIN)
VINUVLO_R VIN UVLO rising threshold VIN rising (needed to start up), IVCC = 0A  3.25 3.5 3.65 V
VINUVLO_F VIN UVLO falling threshold VIN falling (once operating), IVCC = 0A  2.5 2.6 V
VINUVLO_H VIN UVLO hysteresis 0.9 V
IQ_SD VIN shutdown supply current VEN = 0V, TJ = 25℃  0.85 µA
IVIN VIN pin input current, no switching  VBIAS = 3.3V + 2% 0.83 µA
IBIAS(FIX-3.3V) BIAS pin input current, fixed 3.3V output, no switching VBIAS = 3.3V + 2%, Auto Mode enabled  8.0 µA
IQ(FIX-3.3V) Total VIN quiescent current, fixed 3.3V output, no switching VIN = 24V, VBIAS = 3.3V + 2%, TJ = 25℃, Auto Mode enabled  2.1 2.5 µA
TJ = 125℃  3.4 µA
IBIAS(ADJ-3.3V) BIAS pin input current, adjustable 3.3V output, no switching VFB = 0.8V + 2%, Auto Mode 6.5 µA
IQ(ADJ-3.3V) Total VIN quiescent current, adjustable 3.3V output, no switching VIN = 24.0V, VFB = 0.8V + 2%, Auto Mode 2.5 µA
ENABLE (EN PIN)
VEN_TH_R Enable voltage rising threshold VEN rising 1.15 1.25 1.35 V
VEN_TH_F Enable input low threshold VEN falling 0.9 1 1.1 V
VEN_HYS Enable voltage hysteresis 250 mV
IEN_LKG Enable input leakage current VEN = VIN 0.2 1.0 µA
INTERNAL LDO (VCC PIN)
VVCC Internal LDO output voltage 3.4V ≤ VIN ≤ 65V, VBIAS = 0V 3.35 V
3.4V ≤ VBIAS ≤ 30V 3.35 V
VVCC-UVLO_R VCC UVLO rising threshold VCC rising under voltage threshold, IVCC = 0A  3.20 3.5 3.65 V
V VCC-UVLO_H VCC UVLO hysteresis Hysteresis below VVCC-UVLO_R 0.9 V
VOLTAGE REFERENCE (FB PIN)
VFB Internal feedback reference voltage FPWM Mode 0.792 0.8 0.808 V
IFB-LKG Feedback pin input leakage current VFB = 0.8V, adjustable version 0.025 nA
RFB-SEL-5V Resistance for fixed 5.0V setting from FB pin to VCC 200 Ω
RFB-SEL-3V Resistance for fixed 3.3V setting from FB pin to GND 200 Ω
RFB-SEL-ADJ Thevenin equivalent resistance of external FB divider on FB pin to select adjustable output voltage setting 4 100 kΩ
FIXED OUTPUT VOLTAGE (BIAS PIN)
VOUT(3.3V) 3.3V fixed output voltage FB shorted to GND 3.267 3.3 3.333 V
VOUT(5V) 5.0V fixed output voltage FB shorted to VCC 4.95 5 5.05 V
STARTUP (SS PIN)
tEN_HIGH Enable HIGH to start of switching delay VFB = VRT = VMODE = GND,  VBIAS = VOUT 3.0 ms
tSS Internal fixed soft-start time Time from first SW pulse to VREF at 90% of set point 2.9 5.3 8.1 ms
CURRENT LIMITS AND HICCUP
IHS-LIM High side peak current limit, 4.5A trim option Duty cycle approaches 0%. 5.4 6.6 7.25 A
ILS-LIM Low side valley current limit, 4.5A trim option Valley current limit on low-side FET 4.1 5.2 5.65 A
IL-PEAK-MIN Minimum peak inductor current at minimum duty cycle, 4.5A trim option VVCC = 3.3V, tpulse ≤ 100ns, auto mode 1.21 1.57 1.92 A
IL-PEAK-MAX Minimum peak inductor current at maximum duty cycle, 4.5A Trim Option VVCC = 3.3V, tpulse ≥ 1µs, auto mode 0.66 A
IHS-LIM High side peak current limit, 3.5A trim option Duty-cycle approaches 0%. 4.8 5.45 5.9 A
ILS-LIM Low side valley current limit, 3.5A trim option Valley current limit on low-side FET 3.5 4.4 4.85 A
IL-PEAK-MIN Minimum peak inductor current at minimum duty cycle, 3.5A trim option VVCC = 3.3V, tpulse ≤ 100ns, auto mode 0.80 1.29 1.58 A
IL-PEAK-MAX Minimum peak inductor current at maximum duty cycle, 3.5A trim option VVCC = 3.3V, tpulse ≥ 1µs, auto mode 0.52 A
IHS-LIM High side peak current limit, 2.5A trim option Duty-cycle approaches 0%. 3.75 4.1 4.9 A
ILS-LIM Low side valley current limit, 2.5A trim option Valley current limit on low-side FET 2.4 3.0 3.4 A
IL-PEAK-MIN Minimum peak inductor current at minimum duty cycle, 2.5A trim option VVCC = 3.3V, tpulse ≤ 100ns, auto mode 0.8 1.1 1.35 A
IL-PEAK-MAX Minimum peak inductor current at maximum duty cycle, 2.5A trim option VVCC = 3.3V, tpulse ≥ 1µs, auto mode 0.43 A
ILS-NEG-LIM Low side negative current limit, All current limit trim options Sinking current limit on LS FET, FPWM mode –6 –4.3 –2.8 A
IL-ZC-LIM Zero-cross current limit VVCC = 3.3V, auto mode 45 mA
VHIC Overcurrent hiccup threshold on FB pin LS FET on-time > 165ns, not during soft start 0.32 V
tHIC_DLY Hiccup mode activation delay 64 cycles
tHIC Hiccup mode duration time 45 ms
POWER GOOD (PG PIN)
VPG-OVP-R PG overvoltage rising threshold % of FB voltage (Adj) or bias voltage (fixed) 103 105 107 %
VPG-OVP-F PG overvoltage falling threshold % of FB voltage (Adj) or bias voltage (fixed) 101 104 106 %
VPG-UVP-R PG undervoltage rising threshold % of FB voltage (Adj) or bias voltage (fixed) 94 96 98 %
VPG-UVP-F PG undervoltage falling threshold % of FB voltage (Adj) or bias voltage (fixed) 93 95 97 %
tPG-DEGLITCH-F Deglitch filter delay on PG falling edge 55 120 175 µs
tPG-DEGLITCH-R Deglitch filter delay on PG rising edge 1.4 2 4.5 ms
VIN-PG-VALID Minimum VIN for valid PG output VOL(PG) < 0.4V, RPU =  50kΩ, VPU = 5V 1.25 V
VOL-PG Output low voltage IOL = 1mA, VIN = 1.2V 0.4 V
RON-PG PGOOD ON resistance IPG = 1mA 40 125 Ω
SWITCHING FREQUENCY (RT PIN)
fSW1(FPWM) Switching frequency, FPWM operation RRT = GND 1.98 2.2 2.42 MHz
fSW2(FPWM) Switching frequency, FPWM operation RRT = 15.8kΩ, 1% 900 1000 1100 kHz
fSW3(FPWM) Switching frequency, FPWM operation RRT = VCC 360 400 440 kHz
SYNCHRONIZATION (MODE/SYNC PIN)
VIH(MODE/CLKIN) MODE/CLKIN input high level threshold 1.3 V
VIL(MODE/CLKIN) MODE/CLKIN input low level threshold 0.45 V
fCLKIN-RANGE(FPWM) Synchronization frequency range for set 2.2MHz fSW RRT = 6.81kΩ, 1% 1.76 2.64 MHz
tCLKIN(TON) Minimum positive pulse width of external sync signal 80 ns
tCLKIN(TOFF) Minimum negative pulse width of external sync signal 80 ns
tCLKIN-SW-DLY CLKIN to SW delay time(1) –15 15 ns
DUAL RANDOM SPREAD SPECTRUM
ΔfSS1-LF Low-frequency triangular spread spectrum modulation range - standard Mode pin short to ground 8.5 %
ΔfSS2-LF Low-frequency triangular spread spectrum modulation range - extended RMODE = 149.9kΩ, 1% 17 %
fm1-LF Triangular modulation frequency - standard Mode pin short to ground 7.2 12 16.8 kHz
fm2-LF Triangular modulation frequency - extended RMODE = 149.9kΩ, 1% 3.6 6 8.4 kHz
ΔfSS-HF High-frequency pseudo-random spread spectrum modulation range RMODE= 149.9kΩ, 1% 2.0 %
POWER STAGE
RDS-ON-HS High-side FET ON resistance ISW = 500mA, VBOOT-SW = 3.3V 99 mΩ
RDS-ON-LS Low-side FET ON resistance 50 mΩ
tON-MIN(FPWM) Minimum on time(1) FPWM: IOUT = 0A, VIN = 36V, RT = GND 30 40 ns
tON-MIN(AUTO)
Minimum on time(1) 
 		 AUTO: IOUT = 2A, VIN = 36V, RT = GND 28 40 ns
tOFF-MIN Minimum off-time VIN = 4V 80 110 ns
tON-MAX Maximum on-time fSW = 400kHz, RRT= 40.2kΩ 13.3 µs
THERMAL SHUTDOWN
TSD Thermal shutdown(1) Shutdown threshold 155 165 177 ºC
Recovery threshold 156 ºC
(1) Specified by design.