SNOSDC2 September   2021 LM74721-Q1

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reverse Battery Protection (A, C, GATE)
        1. 8.3.1.1 Input TVS Less Operation: VDS Clamp
      2. 8.3.2 Load Disconnect Switch Control (PD)
      3. 8.3.3 Boost Regulator
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Boost Converter Components (C2, C3, L1)
        2. 9.2.2.2 Input and Output Capacitance
        3. 9.2.2.3 Hold-Up Capacitance
        4. 9.2.2.4 MOSFET Selection: Q1
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRR|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • AEC-Q100 qualified with the following results
    • Device temperature grade 1:
      –40°C to +125°C ambient operating temperature range
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • 3-V to 65-V input range
  • Reverse input protection down to –33 V
  • Integrated VDS clamp for Input TVS less operation for ISO7637 pulse suppression
  • Low quiescent current 35 µA (max) in operation
  • Low 3.3-µA (max) shutdown current (EN = Low)
  • Ideal diode operation with 17-mV A to C forward voltage drop regulation
  • Drives external back-to-back N-Channel MOSFETs
  • Integrated 30-mA boost regulator
  • Fast response to reverse current blocking: 0.5 µs
  • Active rectification up to 100 kHz
  • Adjustable overvoltage protection
  • Available in space saving 12-pin WSON package
  • Pin-to-pin compatible with LM74720-Q1