SNOSDC2B September   2021  – July 2022 LM74721-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reverse Battery Protection (A, C, GATE)
        1. 8.3.1.1 Input TVS Less Operation: VDS Clamp
      2. 8.3.2 Load Disconnect Switch Control (PD)
      3. 8.3.3 Overvoltage Protection and Battery Voltage Sensing (VSNS, SW, OV)
      4. 8.3.4 Boost Regulator
    4. 8.4 Shutdown Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Boost Converter Components (C2, C3, L1)
        2. 9.2.2.2 Input and Output Capacitance
        3. 9.2.2.3 Hold-Up Capacitance
        4. 9.2.2.4 MOSFET Selection: Q1
      3. 9.2.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-D4E766DB-F98B-4F88-B475-D6EFDD1D7603-low.gifFigure 5-1 WSON12-Pin DRRTransparent Top View
Table 5-1 Pin Functions
PINTYPEDESCRIPTION
NAMELM74721-Q1
DRR-12 (WSON)
GATE1ODiode controller gate drive output. Connect to the GATE of the external MOSFET.
A2IAnode of the ideal diode. Connect to the source of the external MOSFET.
VSNS3IVoltage sensing input
SW4IVoltage sensing disconnect switch terminal. VSNS and SW are internally connected through a switch. Use SW as the top connection of the battery sensing or OV resistor ladder network. When EN is pulled low, the switch is OFF, disconnecting the resistor ladder from the battery line, thereby cutting off the leakage current. If the internal disconnect switch between VSNS and SW is not used, then short them together and connect to C pin.
OV5IAdjustable overvoltage threshold input. Connect a resistor ladder across SW to OV terminal. When the voltage at OV exceeds the overvoltage cutoff threshold, then the PD is pulled low turning OFF the HSFET. PD is driven high when the sense voltage goes below the OV falling threshold.
EN6IEN Input. Connect to A or C pin for always ON operation. In this mode, the device consumes an IQ of 35 µA (maximum) that can be driven externally from a micro controller I/O. Pulling this pin low below 0.5 V enters the device in low Iq shutdown mode.
GND7GConnect to the system ground plane.
PD8OPull down connection for the external HSFET. Connect to the GATE of the external FET. Leave PD pin floating if the load disconnect FET is not used.
LX9ISwitch node of the internal boost regulator. This node must be kept small on the PCB for good performance and low EMI. Connect the boost inductor between this pin and the DRAIN connection of the external FET.
CAP10OBoost Regulator Output. This pin is used to provide a drive voltage to the gate driver of the ideal diode stage as well as drive supply for the HSFET. Connect a 1-µF capacitor between this pin and the VS pin.
VS11ISupply voltage pin. Place 0.1-µF capacitor from VS pin to GND.
C12ICathode of the ideal diode. Connect to the DRAIN of the external MOSFET. The voltage sensed at this pin is used to control the external MOSFET GATE. This pin must be locally bypassed with at least 1 µF.
RTNThermal Pad—Leave exposed pad floating. Do not connect to GND plane.