SNAS254B October   2006  – April 2017 LM98714

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Timing Specifications
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Clock Introduction
      2. 7.3.2  Modes of Operation
        1. 7.3.2.1 Mode 3 - Three Channel Input/Synchronous Pixel Sampling
        2. 7.3.2.2 Mode 2 - Two Channel Input/Synchronous Pixel Sampling
        3. 7.3.2.3 Mode 1a - One Channel Input/One, Two, Three, Four, or Five Color Sequential Line Sampling
        4. 7.3.2.4 Mode 1b - One Channel Input Per Line/Sequential Line (Input) Sampling/Three Channel Processing
      3. 7.3.3  Input Bias and Clamping
        1. 7.3.3.1 CDS Mode
        2. 7.3.3.2 Input Source Follower Buffers
        3. 7.3.3.3 VCLP DAC
      4. 7.3.4  Coarse Pixel Phase Alignment
      5. 7.3.5  Internal Sample Timing
      6. 7.3.6  Automatic Black Level Correction Loop
        1. 7.3.6.1 Black Level Offset DAC
        2. 7.3.6.2 Black Level Clamp (BLKCLP)
        3. 7.3.6.3 Pixel Averaging
        4. 7.3.6.4 Target Black Level
        5. 7.3.6.5 Offset Integration
        6. 7.3.6.6 Line Averaging
      7. 7.3.7  Internal Timing Generation
        1. 7.3.7.1 Pix Signal Generator OR/NOR Modes
        2. 7.3.7.2 SH2 and SH3 Generation
      8. 7.3.8  CCD Timing Generator Master/Slave Modes
        1. 7.3.8.1 Master Timing Generator Mode
        2. 7.3.8.2 Slave Timing Generator Mode
      9. 7.3.9  LVDS Output Mode
        1. 7.3.9.1 LVDS Output Format
        2. 7.3.9.2 LVDS Output Timing Details
        3. 7.3.9.3 LVDS Control Bit Coding
        4. 7.3.9.4 LVDS Data Latency Diagrams
        5. 7.3.9.5 LVDS Test Modes
          1. 7.3.9.5.1 Test Mode 1 - Worst Case Transitions
          2. 7.3.9.5.2 Test Mode 2 - Ramp
          3. 7.3.9.5.3 Test Mode 3 - Fixed Output Data
      10. 7.3.10 CMOS Output Mode
        1. 7.3.10.1 CMOS Output Data Format
      11. 7.3.11 CMOS Output Data Latency Diagrams
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode 3 - Three Channel Input/Synchronous Pixel Sampling
      2. 7.4.2 Mode 2 - Two Channel Input/Synchronous Pixel Sampling
      3. 7.4.3 Mode 1a - One Channel Input/One, Two, Three, Four, Or Five Color Sequential Line Sampling
      4. 7.4.4 Mode 1b - One Channel Color Input Per Line/Sequential Line (Input) Sampling/Three Channel Processing
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Writing To The Serial Registers
        2. 7.5.1.2 Reading The Serial Registers
        3. 7.5.1.3 Serial Interface Timing Details
    6. 7.6 Register Maps
      1. 7.6.1 Configuration Registers
      2. 7.6.2 Register Definition
  8. 8 Application and Implementation
    1. 8.1 Typical Application
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Device Support
        1. 9.1.1.1 Development Support
      2. 9.1.2 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.