SNAS254B October   2006  – April 2017 LM98714

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Timing Specifications
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Clock Introduction
      2. 7.3.2  Modes of Operation
        1. 7.3.2.1 Mode 3 - Three Channel Input/Synchronous Pixel Sampling
        2. 7.3.2.2 Mode 2 - Two Channel Input/Synchronous Pixel Sampling
        3. 7.3.2.3 Mode 1a - One Channel Input/One, Two, Three, Four, or Five Color Sequential Line Sampling
        4. 7.3.2.4 Mode 1b - One Channel Input Per Line/Sequential Line (Input) Sampling/Three Channel Processing
      3. 7.3.3  Input Bias and Clamping
        1. 7.3.3.1 CDS Mode
        2. 7.3.3.2 Input Source Follower Buffers
        3. 7.3.3.3 VCLP DAC
      4. 7.3.4  Coarse Pixel Phase Alignment
      5. 7.3.5  Internal Sample Timing
      6. 7.3.6  Automatic Black Level Correction Loop
        1. 7.3.6.1 Black Level Offset DAC
        2. 7.3.6.2 Black Level Clamp (BLKCLP)
        3. 7.3.6.3 Pixel Averaging
        4. 7.3.6.4 Target Black Level
        5. 7.3.6.5 Offset Integration
        6. 7.3.6.6 Line Averaging
      7. 7.3.7  Internal Timing Generation
        1. 7.3.7.1 Pix Signal Generator OR/NOR Modes
        2. 7.3.7.2 SH2 and SH3 Generation
      8. 7.3.8  CCD Timing Generator Master/Slave Modes
        1. 7.3.8.1 Master Timing Generator Mode
        2. 7.3.8.2 Slave Timing Generator Mode
      9. 7.3.9  LVDS Output Mode
        1. 7.3.9.1 LVDS Output Format
        2. 7.3.9.2 LVDS Output Timing Details
        3. 7.3.9.3 LVDS Control Bit Coding
        4. 7.3.9.4 LVDS Data Latency Diagrams
        5. 7.3.9.5 LVDS Test Modes
          1. 7.3.9.5.1 Test Mode 1 - Worst Case Transitions
          2. 7.3.9.5.2 Test Mode 2 - Ramp
          3. 7.3.9.5.3 Test Mode 3 - Fixed Output Data
      10. 7.3.10 CMOS Output Mode
        1. 7.3.10.1 CMOS Output Data Format
      11. 7.3.11 CMOS Output Data Latency Diagrams
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode 3 - Three Channel Input/Synchronous Pixel Sampling
      2. 7.4.2 Mode 2 - Two Channel Input/Synchronous Pixel Sampling
      3. 7.4.3 Mode 1a - One Channel Input/One, Two, Three, Four, Or Five Color Sequential Line Sampling
      4. 7.4.4 Mode 1b - One Channel Color Input Per Line/Sequential Line (Input) Sampling/Three Channel Processing
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Writing To The Serial Registers
        2. 7.5.1.2 Reading The Serial Registers
        3. 7.5.1.3 Serial Interface Timing Details
    6. 7.6 Register Maps
      1. 7.6.1 Configuration Registers
      2. 7.6.2 Register Definition
  8. 8 Application and Implementation
    1. 8.1 Typical Application
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Device Support
        1. 9.1.1.1 Development Support
      2. 9.1.2 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

See (1) and (2)
MIN MAX UNIT
Supply voltage (VA,VR,VD,VC) 4.2 V
Voltage on any input pin (not to exceed 4.2 V)(3) –0.3 VA + 0.3 V
Voltage on any output pin (except DVB and not to exceed 4.2 V) –0.3 VA + 0.3 V
DVB output pin voltage 2 V
Input current at any pin other than supply pins(4) ±25 mA
Package input current (except supply pins)(4) ±50 mA
Package dissipation at TA = 25°C(5) 1.89 W
Maximum junction temperature (TA) 150 °C
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to AGND = DGND = 0 V, unless otherwise specified.
(3) The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is limited per note 3. However, input errors will be generated If the input goes above VA and below AGND.
LM98714 20105371.gif
(4) When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to two.
(5) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX – TA)/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (for example, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2500 V
Machine model (MM) 250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

See (1)
MIN NOM MAX UNIT
All supply voltages 3 3.6 V
Operating temperature 0 70 °C
(1) All voltages are measured with respect to AGND = DGND = 0 V, unless otherwise specified.

6.4 Thermal Information

THERMAL METRIC(1) LM98714 UNIT
DGG (TSSOP)
48 PINS
RθJA Junction-to-ambient thermal resistance 66 °C/W
RθJC(top) Junction-to-case (top) thermal resistance — °C/W
RθJB Junction-to-board thermal resistance — °C/W
ψJT Junction-to-top characterization parameter — °C/W
ψJB Junction-to-board characterization parameter — °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

The following specifications apply for VA = VD = VR = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz, TA = 25°C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
CMOS Digital Input DC Specifications (RESETb, SH_R, SCLK, SENb)
VIH Logical 1 input voltage 2 V
VIL Logical 0 input voltage 0.8 V
IIH Logical 1 input current RESET, VIH = VD 235 nA
SH_R, SCLK, VIH = VD 70 μA
SEN, VIH = VD 130 nA
IIL Logical 0 input current RESET, VIL = DGND 70 μA
SH_R, SCLK, VIL = DGND 235 nA
SEN, VIL = DGND 70 μA
CMOS Digital Output DC Specifications (SH, CLK1 to CLK10, CMOS Data Outputs)
VOH Logical 1 output voltage IOUT = –0.5 mA 2.95 V
VOL Logical 0 output voltage IOUT = 1.6 mA 0.25 V
IOS Output short circuit current VOUT = DGND 16 mA
VOUT= VD –20
IOZ CMOS output TRI-STATE current VOUT = DGND 20 nA
VOUT = VD –25
CMOS Digital Input/Output DC Specifications (SDIO)
IIH Logical 1 input current VIH = VD 90 nA
IIL Logical 0 input current VIL = DGND 90 nA
LVDS/CMOS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins)
VIHL Differential LVDS clock
high threshold voltage		 RL = 100 W, VCM (LVDS Input Common Mode Voltage) = 1.25 V 100 mV
VILL Differential LVDS clock
low threshold voltage		 RL = 100 W, VCM (LVDS Input Common Mode Voltage) = 1.25 V –100 mV
VIHC CMOS clock
high threshold voltage		 INCLK- = DGND 2 V
VILC CMOS clock
low threshold voltage		 INCLK- = DGND 0.8 V
IIHL CMOS clock input high current 330 μA
IILC CMOS clock input low current –160 μA
LVDS Output DC Specifications
VOD Differential output voltage RL = 100 Ω 180 328 450 mV
VOS LVDS output offset voltage RL = 100 Ω 1.17 1.23 1.3 V
IOS Output short circuit current VOUT = 0 V, RL = 100 Ω 7.9 mA
Power Supply Specifications
IA VA analog supply current VA Normal State 60 97 125 mA
VA Low Power State (Powerdown) 12 23 32
IR VR digital supply current VR Normal State (LVDS Outputs) 30 64 75 mA
CMOS Output Data Format 15 47 55 mA
LVDS Output Data Format with Data Outputs Disabled 47 mA
ID VD digital output driver supply current LVDS Output Data Format 0.05 mA
CMOS Output Data Format
(ATE Loading of CMOS Outputs > 50 pF)		 12 40 mA
IC VC CCD timing generator output driver supply current Typical sensor outputs: SH, CLK1=Φ1A, CLK2=Φ2A, CLK3=ΦB, CLK4=ΦC, CLK5=RS, CLK6=CP
(ATE Loading of CMOS Outputs > 50 pF)		 0.5 12 mA
PWR Average power dissipation LVDS Output Data Format 350 505 650 mW
CMOS Output Data Format (ATE Loading of CMOS Outputs > 50 pF) 380 610 700 mW
Input Sampling Circuit Specifications
VIN Input voltage level CDS Gain=1x, PGA Gain=1x 2.3 Vp-p
CDS Gain=2x, PGA Gain= 1x 1.22
IIN_SH Sample and hold mode input leakage current Source Followers Off
CDS Gain = 1x
OSX = VA (OSX = AGND)		 50 70 μA
(–70) (–40)
Source Followers Off
CDS Gain = 2x
OSX = VA (OSX = AGND)		 75 105 μA
(–105) (–75)
Source Followers On
CDS Gain = 2x
OSX = VA (OSX = AGND)		 –200 –10 200 nA
–200 –16 200
CSH Sample/hold mode
equivalent input capacitance
(see Figure 5)		 CDS Gain = 1x 2.5 pF
CDS Gain = 2x 4
IIN_CDS CDS mode input leakage current Source Followers Off
OSX = VA (OSX = AGND)		 –300 7 300 nA
–300 (–25) 300
RCLPIN CLPIN switch resistance
(OSX to VCLP Node in Figure 2)		 16 50 Ω
VCLP Reference Circuit Specifications
VCLP DAC resolution 4 Bits
VCLP DAC step size 0.16 V
VVCLP VCLP DAC voltage minimum output VCLP Config.
Register = 0001 0000b		 0.14 0.26 0.43 V
VCLP DAC voltage maximum output VCLP Config.
Register = 0001 1111b		 2.38 2.68 2.93 V
Resistor ladder enabled VCLP Config.
Register = 0010 xxxxb		 1.54 VA / 2 1.73 V
ISC VCLP DAC short circuit output current VCLP Config.
Register = 0001 xxxxb		 30 mA
Black Level Offset DAC Specifications
Resolution 10 Bits
Monotonicity Ensured by characterization
Offset Adjustment Range Referred to AFE Input CDS Gain = 1x
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF		 –614 mV
614
CDS Gain = 2x
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF		 –307 mV
307
Offset adjustment range referred to AFE output Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF		 –16000 –18200 LSB
16000 18200
DAC LSB step size CDS Gain = 1x
Referred to AFE Output		 1.2 mV
(32) (LSB)
DNL Differential nonlinearity –0.95 3.25 LSB
INL Integral nonlinearity –3.1 2.65 LSB
PGA Specifications
Gain Resolution 8 Bits
Monotonicity Ensured by characterization
Maximum gain CDS Gain = 1x 7.18 7.9 8.77 V/V
CDS Gain = 1x 17.1 17.9 18.9 dB
Minimum gain CDS Gain = 1x 0.56 0.7 0.82 V/V
CDS Gain = 1x –5 –3 –1.72 dB
PGA function Gain (V/V) = (196/(280-PGA Code))
Gain (dB) = 20LOG10(196/(280-PGA Code))
Channel matching Minimum PGA Gain 3%
Maximum PGA Gain 12.7%
ADC Specifications
VREFT Top of reference 2.07 V
VREFB Bottom of reference 0.89 V
VREFT - VREFB Differential reference voltage 1.07 1.18 1.29 V
Overrange output code 65535
Underrange output code 0
Digital Offset DAC Specifications
Resolution 7 Bits
Digital offset DAC LSB step size Referred to AFE Output 16 LSB
Offset adjustment range
referred to AFE output		 Min DAC Code =7b0000000 –1024 LSB
Mid DAC Code =7b1000000 0
Max DAC Code = 7b1111111 1008
Full Channel Performance Specifications
DNL Differential nonlinearity –0.99 0.8 / –0.6 2.55 LSB
INL Integral nonlinearity –73 ±23 78 LSB
Noise floor Minimum PGA Gain –79 dB
7.2 LSB RMS
PGA Gain = 1x –74 dB
13 30 LSB RMS
Maximum PGA Gain –56 dB
104 LSB RMS
Channel-to-channel crosstalk Mode 3 47 LSB
Mode 2 16
(1) Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured.

6.6 AC Timing Specifications

The following specifications apply for VA = VD = VR = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz, TA = 25°C, unless otherwise specified.
MIN TYP(1) MAX UNIT
Input Clock Timing Specifications
fINCLK Input Clock Frequency Mode 3, INCLK = PIXCLK (Pixel Rate Clock) 15 MHz
Mode 2, INCLK = PIXCLK (Pixel Rate Clock) 22.5
Mode 1, INCLK = PIXCLK (Pixel Rate Clock) 30
Mode 3, INCLK = ADCCLK (ADC Rate Clock) 5 45 MHz
Mode 2, INCLK = ADCCLK (ADC Rate Clock) 5 45
Mode 1, INCLK = ADCCLK (ADC Rate Clock) 5 30
Tdc Input Clock Duty Cycle 40/60% 50/50% 60/40%
Full Channel Latency Specifications
tSHFP SH out to first sampled pixel PIXPHASE0 3 TADC
Figure 11 (Mode 3) PIXPHASE1 3 3/7
Figure 12 (Mode 2) PIXPHASE2 4
Figure 13 (Mode 1) PIXPHASE3 4 3/7
tLAT3 3 channel mode pipeline delay
Figure 45 (LVDS)
Figure 50 (CMOS)		 PIXPHASE0 19 TADC
PIXPHASE1 18 4/7
PIXPHASE2 18
PIXPHASE3 17 4/7
tLAT2 2 channel mode pipeline delay
Figure 46 (LVDS)
Figure 51(CMOS)		 PIXPHASE0 18 TADC
PIXPHASE1 17 4/7
PIXPHASE2 17
PIXPHASE3 16 4/7
tLAT1 1 channel mode pipeline delay
Figure 47 (LVDS)
Figure 52(CMOS)
 PIXPHASE0 16 TADC
PIXPHASE1 15 4/7
PIXPHASE2 15
PIXPHASE3 14 4/7
tSHFD SH out to first valid data
(tSHFP + tLATx)		 Mode 3 22 TADC
Mode 2 21
Mode 1 19
SH_R Timing Specifications (Figure 41)
tSHR_S SH_R setup time 1.28 ns
tSHR_H SH_R hold time 2.25 ns
LVDS Output Timing Specifications (Figure 44)
TXvalid TX output data valid window fINCLK = 45 MHz
INCLK = ADCCLK
(ADC Rate Clock)		 2 ns
TXpp0 TXCLK to pulse position 0 LVDS Output
Specifications not tested in production.
Min/Max ensured by design, characterization and statistical analysis.		 0.013 ns
TXpp1 TXCLK to pulse position 1 3.093 ns
TXpp2 TXCLK to pulse position 2 6.238 ns
TXpp3 TXCLK to pulse position 3 9.613 ns
TXpp4 TXCLK to pulse position 4 12.663 ns
TXpp5 TXCLK to pulse position 5 15.762 ns
TXpp6 TXCLK to pulse position 6 18.982 ns
CMOS Output Timing Specifications
tCRDO CLKOUT rising edge to CMOS output data fINCLK = 45 MHz, INCLK = ADCCLK, (ADC Rate Clock) –2.83 2.7 ns
tCFDO CLKOUT Falling edge to CMOS output data fINCLK = 45 MHz, INCLK = ADCCLK, (ADC Rate Clock) –2.83 2.7 ns
Serial Interface Timing Specifications
fSCLK Input clock frequency fSCLK ≤ fINCLK
INCLK = PIXCLK
(Pixel Rate Clock)
Mode 3/2/1		 15/22.5/30 MHz
fSCLK ≤ fINCLK
INCLK = ADCCLK
(ADC Rate Clock)
Mode 3/2/1		 45/45/30 MHz
SCLK duty cycle 50/50 ns
tIH Input hold time 1 ns
tIS Input setup time 4 ns
tSENSC SCLK start time after SEN low 1.25 ns
tSCSEN SEN high after last SCLK rising edge 2.82 ns
tSENW SEN pulse width INCLK must be active during serial interface commands. 4 TINCLK
tOD Output delay time 11 14.6 ns
tHZ Data output to High Z 0.5 TSCLK
(1) Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured.

6.7 Typical Characteristics

LM98714 PGA_Gain_vs_PGA_Gain_Mode.gif Figure 1. PGA Gain vs. PGA Gain Code