SNOS630E August   2000  – February 2024 LMC6081 , LMC6082 , LMC6084

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information LMC6081
    5. 5.5 Thermal Information LMC6082
    6. 5.6 Thermal Information LMC6084
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Amplifier Topology
      2. 6.1.2 Compensating for Input Capacitance
      3. 6.1.3 Capacitive Load Tolerance
      4. 6.1.4 Latch-Up
    2. 6.2 Typical Applications
      1. 6.2.1 Typical Single-Supply Applications
      2. 6.2.2 Instrumentation Amplifier
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 Printed Circuit Board Layout for High-Impedance Work
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1.4 Latch-Up

CMOS devices tend to be susceptible to latch-up as a result of the internal, parasitic, silicon-controlled rectifier (SCR) effects. The input and output (I/O) pins look similar to the gate of the SCR. A minimum current is required to trigger the SCR gate lead. Use some resistive method to isolate any capacitance from supplying excess current to the I/O pins. In addition, like an SCR, there is a minimum holding current for any latch-up mode. Limiting current to the supply pins also inhibits latch-up susceptibility.