SNOS725E May   1999  – March 2025 LMC6462 , LMC6464

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for LMC6462
    5. 5.5 Thermal Information for LMC6464
    6. 5.6 Electrical Characteristics for VS = ±2.25V or VS = 5V
    7. 5.7 Electrical Characteristics for VS = ±1.5V or VS = 3V
  7. 6 Typical Characteristics
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input Common-Mode Voltage Range
      2. 7.1.2 Rail-to-Rail Output
      3. 7.1.3 Capacitive Load Tolerance
      4. 7.1.4 Compensating for Input Capacitance
      5. 7.1.5 Offset Voltage Adjustment
      6. 7.1.6 Instrumentation Circuits
    2. 7.2 Typical Applications
      1. 7.2.1 Transducer Interface Circuits
      2. 7.2.2 LMC646x as a Comparator
      3. 7.2.3 Half-Wave and Full-Wave Rectifiers
      4. 7.2.4 Precision Current Source
      5. 7.2.5 Oscillators
      6. 7.2.6 Low Frequency Null
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
        1. 7.3.1.1 PCB Layout for High-Impedance Work
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
    2. 8.2 Documentation Support
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • N|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics for VS = ±1.5V or VS = 3V

at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOUT = V+ / 2, and RL > 1MΩ connected to V+ / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage LMC646xA ±0.9 ±2 mV
TA = –40°C to +85°C ±2.7
LMC646xB ±0.9 ±3
TA = –40°C to +85°C ±3.7
dVOS/dT Input offset voltage drift TA = –40°C to +85°C 2 µV/°C
PSRR Power-supply rejection ratio 3V ≤ V+ ≤ 15V 60 80 dB
INPUT BIAS CURRENT
IB Input bias current(1) ±0.15 pA
TA = –40°C to +85°C ±10
IOS Input offset current(1) ±0.075 pA
TA = –40°C to +85°C ±5
NOISE
en Input voltage noise density f = 1kHz, VCM = 1V 80 nV/√Hz
in Input current noise density f = 1kHz 30 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage range To positive rail
V+ = 5V, CMRR ≥ 50dB		 3 3 V
To negative rail
V+ = 5V, CMRR ≥ 50dB		 –0.1 0
CMRR Common-mode rejection ratio 0V ≤ VCM ≤ 3V 60 74 dB
FREQUENCY RESPONSE
GBW Gain bandwidth product 50 kHz
SR Slew rate(2) G = 1, 2V step 23 V/ms
OUTPUT
VO Voltage output swing Positive rail
RL = 25kΩ to V+ / 2		 2.95 2.9 V
Negative rail
RL = 25kΩ to V+ / 2		 0.1 0.15 V
POWER SUPPLY
IQ Quiescent current VOUT = V+ / 2 LMC6462 40 55 µA
LMC6462, TA = –40°C to +85°C 70
LMC6464 80 110
LMC6464, TA = –40°C to +85°C 140
(1) Specified limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
(2) Number specified is the slower of either the positive or negative slew rates.