SLUSFB3 November   2023 LMG3616

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 GaN Power FET Switching Capability
      2. 7.3.2 Turn-On Slew-Rate Control
      3. 7.3.3 Input Control Pin (IN)
      4. 7.3.4 AUX Supply Pin
        1. 7.3.4.1 AUX Power-On Reset
        2. 7.3.4.2 AUX Under-Voltage Lockout (UVLO)
      5. 7.3.5 Overtemperature Protection
      6. 7.3.6 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Turn-On Slew-Rate Design
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REQ|38
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 GaN Power FET Switching Parameters

Figure 6-1 shows the circuit used to measure the GaN power FET switching parameters. The circuit is operated as a double-pulse tester. Consult external references for double-pulse tester details. The circuit operates in the boost configuration with the low-side LMG3616 being the device under test (DUT). The high-side LMG3616 acts as the double-pulse tester diode and circulates the inductor current in the off-state, third-quadrant conduction mode.


GUID-20231109-SS0I-P3H7-KGGJ-8D6LXSHJM921-low.svg

Figure 6-1 GaN Power FET Switching Parameters Test Circuit

Figure 6-2 shows the GaN power FET switching parameters.

The GaN power FET turn-on transition has three timing components: drain-current turn-on delay time, turn-on delay time, and turn-on rise time. Note that the turn-on rise time is the same as the VDS 80% to 20% fall time. All three turn-on timing components are a function of the RDRV pin setting.

The GaN power FET turn-off transition has two timing components: turn-off delay time, and turn-off fall time. Note that the turn-off fall time is the same as the VDS 20% to 80% rise time. The turn-off timing components are independent of the RDRV pin setting, but heavily dependent on the LHB current.

The turn-on slew rate is measured over a smaller voltage delta (100 V) compared to the turn-on rise time voltage delta (240 V) to obtain a faster slew rate which is useful for EMI design. The RDRV pin is used to program the slew rate.


GUID-20230815-SS0I-54L1-4JCL-1V4LNLZ7BMGG-low.svg

Figure 6-2 GaN Power FET Switching Parameters