SNLS270L August   2007  – January 2016 LMH0356

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 AC Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Functional Block Description
        1. 8.3.1.1 Serial Data Input and Outputs
        2. 8.3.1.2 Operating Serial Data Rates
        3. 8.3.1.3 Serial Data Clock/Serial Data 2 Output
      2. 8.3.2 Control Inputs and Indicator Outputs
        1. 8.3.2.1 Serial Data Rate Selector
        2. 8.3.2.2 Serial Data Input Selector
        3. 8.3.2.3 Lock Detect
        4. 8.3.2.4 OUTPUT MUTE
        5. 8.3.2.5 Bypass/AUTO BYPASS
        6. 8.3.2.6 SD/HD
        7. 8.3.2.7 SCO_EN
        8. 8.3.2.8 ENABLE
        9. 8.3.2.9 Crystal or External Clock Reference
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Output Interfacing
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage (VCC – VEE) 4 v
Logic supply voltage VEE – 0.15 VCC + 0.15 V
Logic input current (single input) Vi = VEE – 0.15 V –5 mA
Vi = VCC + 0.15 V 5
Logic output voltage VEE – 0.15 VCC + 0.15 V
Logic output source/sink current –8 8 mA
Serial data output sink current 24 mA
Junction temperature (TJ) 125 °C
Storage temperature (Tstg) –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±8000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1250
Machine model (MM) ±400
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±8000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1250 V may actually have higher performance.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage 3.3 – 5% 3.3 + 5% V
Logic input voltage VEE VCC V
Differential serial input voltage 800 – 10% 800 + 10% mV
Serial data or clock output sink current 16 mA
Operating free-air temperature –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) LMH0356 UNIT
RHS (WQFN) RSB (WQFN)
48 PINS 40 PINS
RθJA Junction-to-ambient thermal resistance 28.3 31.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 8.8 16.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.3 1.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

7.5 DC Electrical Characteristics

over supply voltage and recommended operating temperature ranges (unless otherwise noted)(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Logic input voltage high level 2 VCC V
VIL Logic input voltage low level VEE 0.8 V
IIH Logic input current high level VIH = VCC 47 65 µA
IIL Logic input current low level VIL = VEE −18 −25 µA
VOH Logic output voltage high level IOH = −2 mA 2 V
VOL Logic output voltage low level IOL = 2 mA VEE + 0.6 V
VSDID Serial input voltage, differential  SDI (7) 200 1600 mVP-P
VCMI Input common mode voltage VSDID = 200 mV (7) VEE + 0.95 VCC − 0.2 V
VSDOD Serial data output voltage, differential SDO, SDO2 100-Ω differential load 620 750 880 mVP-P
VSCOD Serial clock output voltage, differential SCO 100-Ω differential load, 2970 MHz (7) 400 525 650 mVP-P
SCO 100-Ω differential load, 1485 or 270 MHz 750 mVP-P
VCMO Output common mode voltage SDO, SCO 100-Ω differential load VCC − VSDOD V
ICC Power supply current, 3.3-V supply, total 2970 Mbps, device enabled 130 150 mA
Device disabled
(ENABLE = 0)		 3 mA

7.6 AC Electrical Characteristics

over supply voltage and recommended operating temperature ranges (unless otherwise noted)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BRSD Serial data rate ST-259 270 Mbps
BRSD Serial data rate ST-292 1483, 1485 Mbps
BRSD Serial data rate ST-424 2967, 2970 Mbps
TOLJIT Serial input jitter tolerance 270 Mbps(6)(7)(8) >6 UIP-P
TOLJIT Serial input jitter tolerance 270 Mbps(6)(7)(9) >0.6 UIP-P
TOLJIT Serial input jitter tolerance 1483 or 1485 Mbps(6)(7)(8) >6 UIP-P
TOLJIT Serial input jitter tolerance 1483 or 1485 Mbps(6)(7)(9) >0.6 UIP-P
TOLJIT Serial input jitter tolerance 2967 or 2970 Mbps(6)(7)(8) >6 UIP-P
TOLJIT Serial input jitter tolerance 2967 or 2970 Mbps
(6) (7) (9)		 >0.6 UIP-P
tJIT Serial data output jitter 270 Mbps(7)(10) 0.01 0.03 UIP-P
tJIT Serial data output jitter 1483 or 1485 Mbps(7)(11) 0.04 0.05 UIP-P
tJIT Serial data output jitter 2967 or 2970 Mbps(7)(12) 0.08 0.09 UIP-P
BWLOOP Loop bandwidth 270-Mbps,
<0.1-dB Peaking		 275 kHz
1485-Mbps,
<0.1-dB Peaking		 1.5 MHz
2970 Mbps,
<0.1-dB Peaking		 2.75 MHz
FCO Serial clock output frequency 270-Mbps data rate 270 MHz
FCO Serial clock output frequency 1483-Mbps data rate 1483 MHz
FCO Serial clock output frequency 1485-Mbps data rate 1485 MHz
FCO Serial clock output frequency 2967-Mbps data rate 2967 MHz
FCO Serial clock output frequency 2970-Mbps data rate 2970 MHz
tJIT Serial Clock Output Jitter 2 3 psRMS
SCALG Serial clock output alignment with respect to data interval See (7) 40% 60%
SCODC Serial clock output duty cycle See (7) 45% 55%
FREF Reference clock frequency 27 MHz
FTOL Reference clock frequency tolerance ±50 ppm
(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VEE (equal to zero volts).
(2) Typical values are stated for: VCC = 3.3 V, TA = 25°C.
(3) This specification is ensured by design.
(4) RL = 100-Ω differential.
(5) Measured from first SDI transition until Lock Detect output goes high (true).
(6) Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars.
(7) This parameter is ensured by characterization over voltage and temperature limits.
(8) Refer to A1 in Figure 1 of SMPTE RP 184-1996.
(9) Refer to A2 in Figure 1 of SMPTE RP 184-1996.
(10) PRBS 210– 1, input jitter = 31 psP-P.
(11) PRBS 210– 1, input jitter = 24 psP-P.
(12) PRBS 210– 1, input jitter = 22 psP-P.

7.7 AC Timing Requirements

MIN NOM MAX UNIT
TACQ Acquisition time See (5) 15 ms
tr, tf Logic inputs rise/fall time 10%–90% 1.5 ns
tr, tf Input rise/fall time 20%–80%, 270 Mbps (3) 1500 ps
tr, tf Input rise/fall time 20%–80%, 1483 or 1485 Mbps (3) 270 ps
tr, tf Input rise/fall time 20%–80%, 2967 or 2970 Mbps (3) 135 ps
tr, tf Logic outputs rise/fall time 10%–90% 1.5 ns
tr, tf Output rise/fall time 20%–80% (4) (7) 90 130 ps
LMH0356 30016705.gif
TACQ = Acquisition Time, defined in AC Timing Requirements
T1 = Time from Lock Detect assertion or deassertion until SD/HD output is valid, typically 37 ns (one 27-MHz clock period)
T2 = Time from SDI input change until Lock Detect deassertion, 1 ms maximum. SD/HD output is not valid during this time.
Figure 1. SDI, Lock Detect, and SD/HD Timing