SNLS474E February   2015  – June 2018 LMH1218

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified SPI Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD
    2.     Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Loss of Signal Detector
      2. 7.3.2 Continuous Time Linear Equalizer (CTLE)
      3. 7.3.3 2:1 Multiplexer
      4. 7.3.4 Clock and Data Recovery
      5. 7.3.5 Eye Opening Monitor (EOM)
      6. 7.3.6 Fast EOM
        1. 7.3.6.1 SMBus Fast EOM Operation
        2. 7.3.6.2 SPI Fast EOM Operation
      7. 7.3.7 LMH1218 Device Configuration
        1. 7.3.7.1 MODE_SEL
        2. 7.3.7.2 ENABLE
        3. 7.3.7.3 LOS_INT_N
        4. 7.3.7.4 LOCK
        5. 7.3.7.5 SMBus MODE
        6. 7.3.7.6 SMBus READ/WRITE Transaction
        7. 7.3.7.7 SPI Mode
          1. 7.3.7.7.1 SPI READ/WRITE Transaction
          2. 7.3.7.7.2 SPI Write Transaction Format
          3. 7.3.7.7.3 SPI Read Transaction Format
        8. 7.3.7.8 SPI Daisy Chain
          1. 7.3.7.8.1 SPI Daisy Chain Write Example
          2. 7.3.7.8.2 SPI Daisy Chain Write Read Example
            1. 7.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
      8. 7.3.8 Power-On Reset
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 Global Registers
      2. 7.6.2 Receiver Registers
      3. 7.6.3 CDR Registers
      4. 7.6.4 Transmitter Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for All Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Initialization Set Up
      1. 8.4.1 Selective Data Rate Lock
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Solder Profile
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.4 Transmitter Registers

Table 8. Transmitter Registers

REGISTER NAME BITS FIELD REGISTER ADDRESS DEFAULT R/RW DESCRIPTION
Out0_Mux_Select Reg 0x1C Channel 0x18 OUT0 Mux Selection
7 pfd_sel0_data_mux[2] 0 RW When 0x09[5] = 1'b OUT0 Mux Selection can be controlled as follows:
000: Mute
001: 10 MHz Clock
010: Raw Data
100: Retimed Data
Other Settings - Invalid
6 pfd_sel0_data_mux[1] 0 RW
5 pfd_sel0_data_mux[0] 0 RW
4 VCO_Div40 1 RW When 0x09[5] = 1'b and 0x1E[[7:5] = 101'b OUT1 clock selection can be controlled as follows:
1: OUT1 puts out line rate clock for 3G and below and 297 MHz clock for 5.94 Gbps and 11.88Gbps
0: OUT1 puts out 10MHz clock
3 mr_drv_out_ctrl[1] 1 RW Controls both OUT0 and OUT1:
00:
OUT0: Mute
OUT1: Mute
01:
OUT0: Locked Reclocked Data / Unlocked Raw Data
OUT1: Locked Output Clock / Unlocked Mute
10:
OUT0: Locked Reclocked Data / Unlocked RAW
OUT1: Locked Reclocked Data / Unlocked Raw
11:
OUT0: Forced Raw
OUT1: Forced Raw
2 mr_drv_out_ctrl[0] 0 RW
1 Reserved 0 RW
0 Reserved 0 RW
OUT1_Mux_Select Reg 0x1E Channel 0xE9 OUT1 Mux Selection
7 pfd_sel_data_mux[2] 1 RW When 0x09[5] = 1'b OUT0 Mux Selection can be controlled as follows:
111: Mute
101: 10MHz Clock if reg 0x1c[4]=0 and divided by 40 if reg 0x1c[4] = 1
010: Full Rate Clock
001: Retimed Data
000: Raw Data
Other Settings - Invalid
6 pfd_sel_data_mux[1] 1 RW
5 pfd_sel_data_mux[0] 1 RW
4 Reserved 0 RW
3 Reserved 1 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 1 RW
OUT1 Invert Reg 0x1F Channel 0x10 Invert OUT1 Polarity
7 pfd_sel_inv_out1 0 RW 1: Inverts OUT1 polarity
0: OUT1 Normal polarity
6 Reserved 0 RW
5 Reserved 0 RW
4 Reserved 1 RW
3 Reserved 0 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 0 RW
OUT0_VOD Reg 0x80 Channel 0x20 OUT0 VOD_Scaling_PD
7 drv_0_sel_vod[3] 0 RW drv_0_sel_vod[3:0] is typically 42 mV per step. Refer to the LMH1218 Programming Guide (SNLU174) for setting OUT0 VOD
6 drv_0_sel_vod[2] 0 RW
5 drv_0_sel_vod[1] 1 RW
4 drv_0_sel_vod[0] 0 RW
3 Reserved 0 RW
2 Reserved 0 RW
1 mr_drv_0_ov 0 RW 1: Enable 0x80[0] to override pin/sm control
0: Disable 0x80[0] to override pin/sm control
0 sm_drv_0_PD 0 RW 1: Power down OUT0
0: OUT1 in normal operating mode
OUT1_VOD Reg 0x84 Channel 0x04 OUT1 VOD Control
7 Reserved 0 RW
6 drv_1_sel_vod[2] 0 RW OUTDriver1 VOD Setting
000: 570 mVDifferential(Diff) Peak to Peak(PP)
010: 730 mV(Diff PP)
100: 900 mV(Diff PP)
110: 1035 mV(Diff PP)
5 drv_1_sel_vod[1] 0 RW
4 drv_1_sel_vod[0] 0 RW
3 Reserved 0 RW
2 drv_1_sel_scp 1 RW 1: Enables short circuit protection on OUT1
0: Disable short circuit protection on OUT1
1 mr_drv_1_ov 0 RW 1: Enable 0x80[0] to override pin/sm control
0: Disable 0x80[0] to override pin/sm control
0 sm_drv_1_PD 0 RW 1: Power down OUT1 driver
0: OUT1 in normal operating mode
OUT1_DE Reg 0x85 0x00 OUT1 DE Control
7 Reserved 0 RW
6 Reserved 0 RW
5 Reserved 0 RW
4 Reserved 0 RW
3 drv_1_dem_range 0 RW Controls de-emphasis of 50 Ω Driver
0000: DE Disabled
0001: 0.2 dB
0010: 1.8 dB
0111: 11 dB
2 drv_1_dem[2] 0 RW
1 drv_1_dem[1] 0 RW
0 drv_1_dem[0] 0 RW