SBOSA63A December   2020  – November 2021 LMH32404-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics: Logic Threshold and Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clamping and Input Protection
      2. 7.3.2 ESD Protection
      3. 7.3.3 Differential Output Stage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ambient Light Cancellation (ALC) Mode
      2. 7.4.2 Channel Multiplexer Mode
      3. 7.4.3 Low-Power Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Standard TIA Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Increase Channel Density for Optical Front-End Systems
        1. 8.2.2.1 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Application Information

Each differential output pair of the LMH32404-Q1 can directly drive a high-speed differential input ADC. Figure 8-1 shows how the effective signal the effective signal gain between the TIA input and the ADC input is 20 kΩ when driving an ADC with a 100-Ω differential input impedance (RADC_IN = 50 Ω). Equation 2 gives the effective signal gain between the TIA input and the ADC input when driving an ADC with any other value of differential input impedance (RADC_IN ≠ 50 Ω).

Figure 8-1 LMH32404-Q1 (Single Channel) to ADC Interface
Equation 2. GUID-20201105-CA0I-NBW7-JF62-KQJMT02WGNHF-low.gif

where

  • AV = Differential gain from the TIA input to the ADC input
  • RADC_IN = Input resistance of the ADC

Figure 8-2 shows that in some designs a matching resistor network can be inserted between the LMH32404-Q1 output and the ADC inputs. Equation 3 gives the effective gain from the TIA input to the ADC input when using a matching resistor network.

Figure 8-2 LMH32404-Q1 (Single Channel) to ADC Interface With a Matching Resistor Network
Equation 3. GUID-20201105-CA0I-WVKK-KXX5-ZHV2SRLBXZDK-low.gif

where

  • AV = Gain from the TIA input to the ADC input
  • RADC_IN = Differential input resistance of the ADC
  • RISO = Series resistance between the TIA and ADC

Equation 4 gives the voltage to be applied at the VOD pin (pin 10) if a certain differential offset voltage (VOD) is needed at the ADC input for the circuit in Figure 8-2.

Equation 4. GUID-45965872-B14D-409C-8CFF-AB6A0997F65E-low.gif

where

  • VOD = Voltage applied at pin 10
  • VOD = Desired differential offset voltage at the ADC input
  • RADC_IN = Differential input resistance of the ADC
  • RISO = Series resistance between the TIA and ADC