SNAS512J september   2011  – may 2023 LMK00301

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  10. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VCC and VCCO Power Supplies
    4. 9.4 Device Functional Modes
      1. 9.4.1 Clock Inputs
      2. 9.4.2 Clock Outputs
        1. 9.4.2.1 Reference Output
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Driving the Clock Inputs
        2. 10.2.1.2 Crystal Interface
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Termination and Use of Clock Drivers
          1. 10.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 10.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 10.2.2.1.3 Termination for Single-Ended Operation
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Current Consumption and Power Dissipation Calculations
      1. 11.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
      2. 11.2.2 Power Dissipation Example #2: Worst-Case Dissipation
    3. 11.3 Power Supply Bypassing
      1. 11.3.1 Power Supply Ripple Rejection
    4. 11.4 Thermal Management
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Driving the Clock Inputs

The LMK00301 has two universal inputs (CLKin0/CLKin0* and CLKin1/CLKin1*) that can accept AC-coupled or DC-coupled, 3.3-V or 2.5-V LVPECL, LVDS, CML, SSTL, and other differential and single-ended signals that meet the input requirements specified in Electrical CharacteristicsElectrical CharacteristicsElectrical CharacteristicsElectrical Characteristics . The device can accept a wide range of signals due to its wide input common-mode voltage range (VCM ) and input voltage swing (VID) / dynamic range. For 50% duty cycle and DC-balanced signals, AC coupling may also be employed to shift the input signal to within the VCM range. Refer to Termination and Use of Clock DriversTermination and Use of Clock DriversTermination and Use of Clock Drivers for signal interfacing and termination techniques.

To achieve the best possible phase noise and jitter performance, it is mandatory for the input to have high slew rate of 3 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter. For this reason, TI recommends a differential signal input over a single-ended signal because this signal typically provides higher slew rate and common-mode-rejection. See the Noise Floor vs CLKin Slew Rate and RMS Jitter vs CLKin Slew Rate plots in Typical CharacteristicsTypical Characteristics section.

While TI recommends to drive the CLKin/CLKin* pair with a differential signal input, it is possible to drive the pair with a single-ended clock, provided the clock conforms to the Single-Ended Input specifications for CLKin pins listed in the Electrical CharacteristicsElectrical CharacteristicsElectrical CharacteristicsElectrical Characteristics. For large single-ended input signals, such as 3.3-V or 2.5-V LVCMOS, place a 50-Ω load resistor near the input for signal attenuation to prevent input overdrive as well as for line termination to minimize reflections. Again, the single-ended input slew rate should be as high as possible to minimize performance degradation. The CLKin input has an internal bias voltage of about 1.4 V, so the input can be AC coupled as shown in Figure 10-2. The output impedance of the LVCMOS driver plus Rs should be close to 50 Ω to match the characteristic impedance of the transmission line and load termination.

GUID-EDCDAD8E-1859-4291-9F50-7C2532DD6E4A-low.gifFigure 10-2 Single-Ended LVCMOS Input, AC Coupling

A single-ended clock may also be DC coupled to CLKinX as shown in Figure 10-3. Place a 50-Ω load resistor near the CLKinX input for signal attenuation and line termination. Half of the single-ended swing of the driver (VO,PP / 2) drives CLKinX, therefore CLKinX* should be externally biased to the midpoint voltage of the attenuated input swing ((VO,PP / 2) × 0.5). The external bias voltage should be within the specified input common-mode voltage (VCM) range. This can be achieved using external biasing resistors in the kΩ range (RB1 and RB2) or another low-noise voltage reference. This will ensure the input swing crosses the threshold voltage at a point where the input slew rate is the highest.

If the LVCMOS driver cannot achieve sufficient swing with a DC-terminated, 50-Ω load at the CLKinX input as shown in Figure 10-3, then consider connecting the 50-Ω load termination to ground through a capacitor (CAC). This AC termination blocks the DC load current on the driver, so the voltage swing at the input is determined by the voltage divider formed by the source (Ro+Rs) and 50-Ω load resistors. The value for CAC depends on the trace delay, Td, of the 50-Ω transmission line;

Equation 1. CAC ≥ 3 × Td / 50 Ω
GUID-8CE58365-A034-4101-ADF7-EEBA4717A9E1-low.gifFigure 10-3 Single-Ended LVCMOS Input, DC Coupling with Common-Mode Biasing

If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external clock as shown in Figure 10-4. The input clock should be AC coupled to the OSCin pin, which has an internally-generated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alternative input to multiplex an external clock, TI recommends to use either universal input (CLKinX) because the inputs offer higher operating frequency, better common-mode and power supply noise rejection, and greater performance over supply voltage and temperature variations.

GUID-0BED3F99-CF83-47FD-B556-B97219F3D2B0-low.gifFigure 10-4 Driving OSCin with a Single-Ended Input