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LMK00301

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3-GHz, 10-output differential fanout buffer / level translator

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Data sheet

LMK00301

ACTIVE
Data sheet Order now

Product details

Number of outputs 11 Additive RMS jitter (typ) (fs) 51 Core supply voltage (V) 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVDS, LVPECL Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL
Number of outputs 11 Additive RMS jitter (typ) (fs) 51 Core supply voltage (V) 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVDS, LVPECL Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL
WQFN (RHS) 48 49 mm² 7 x 7
  • 3:1 input multiplexer
    • Two universal inputs operate up to 3.1GHz and accept lvpecl, lvds, cml, sstl, hstl, hcsl, or single-ended clocks
    • One crystal input accepts 10MHz to 40Mhz crystal or single-ended clock
  • Two banks with five differential outputs each
    • LVPECL, LVDS, HCSL, or Hi-Z (selectable per bank)
    • LVPECL additive jitter with LMK03806 clock source at 156.25MHz:
      • 20 fs RMS (10kHz to 1MHz)
      • 51 fs RMS (12kHz to 20MHz)
  • Frequency range:
    • LVPECL (DC to 3100MHz)
    • LVDS (DC to 2100MHz)
    • HCSL (DC to 800MHz)
    • LVCMOS (DC to 250MHz)
  • Additive RMS Jitter after PCIe Filters:
    • Gen 7: 9.38fs (LVPECL), 10.1fs (HCSL), 12.6fs (LVDS) (maxima)
    • Gen 6: 13.4fs (LVPECL), 14.3fs (HCSL), 18.0fs (LVDS) (maxima)
    • Gen 5: 21.8fs (LVPECL), 23.6fs (HCSL), 30.3fs (LVDS) (maxima)
  • High PSRR: –65dBc (LVPECL) and –76dBc (LVDS) at 156.25MHz
  • LVCMOS output with synchronous enable input
  • Pin-controlled configuration
  • VCC core supply: 3.3V ± 5%
  • Three independent VCCO output supplies: 3.3V or 2.5V ± 5%
  • Industrial temperature range: –40°C to +85°C
  • 3:1 input multiplexer
    • Two universal inputs operate up to 3.1GHz and accept lvpecl, lvds, cml, sstl, hstl, hcsl, or single-ended clocks
    • One crystal input accepts 10MHz to 40Mhz crystal or single-ended clock
  • Two banks with five differential outputs each
    • LVPECL, LVDS, HCSL, or Hi-Z (selectable per bank)
    • LVPECL additive jitter with LMK03806 clock source at 156.25MHz:
      • 20 fs RMS (10kHz to 1MHz)
      • 51 fs RMS (12kHz to 20MHz)
  • Frequency range:
    • LVPECL (DC to 3100MHz)
    • LVDS (DC to 2100MHz)
    • HCSL (DC to 800MHz)
    • LVCMOS (DC to 250MHz)
  • Additive RMS Jitter after PCIe Filters:
    • Gen 7: 9.38fs (LVPECL), 10.1fs (HCSL), 12.6fs (LVDS) (maxima)
    • Gen 6: 13.4fs (LVPECL), 14.3fs (HCSL), 18.0fs (LVDS) (maxima)
    • Gen 5: 21.8fs (LVPECL), 23.6fs (HCSL), 30.3fs (LVDS) (maxima)
  • High PSRR: –65dBc (LVPECL) and –76dBc (LVDS) at 156.25MHz
  • LVCMOS output with synchronous enable input
  • Pin-controlled configuration
  • VCC core supply: 3.3V ± 5%
  • Three independent VCCO output supplies: 3.3V or 2.5V ± 5%
  • Industrial temperature range: –40°C to +85°C

The LMK00301 is a 3GHz, 10-output differential fanout buffer intended for high-frequency, low-jitter clock and data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of five differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00301 operates from a 3.3V core supply and three independent 3.3V or 2.5V output supplies.

The LMK00301 provides high performance, versatility, and power efficiency, making the device designed for replacing fixed-output buffer devices while increasing timing margin in the system. The LMK00301 offers a design spin, the LMK00301A, that does not have power supply sequencing requirements between the core and output supply domains.

The LMK00301 is a 3GHz, 10-output differential fanout buffer intended for high-frequency, low-jitter clock and data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of five differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00301 operates from a 3.3V core supply and three independent 3.3V or 2.5V output supplies.

The LMK00301 provides high performance, versatility, and power efficiency, making the device designed for replacing fixed-output buffer devices while increasing timing margin in the system. The LMK00301 offers a design spin, the LMK00301A, that does not have power supply sequencing requirements between the core and output supply domains.
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* Data sheet LMK00301 3GHz 10-Output Ultra-Low Additive Jitter Differential Clock Buffer and Level Translator datasheet (Rev. K) PDF | HTML 24 Oct 2025
Application note Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 03 Sep 2024
Application note Clocking for PCIe Applications PDF | HTML 28 Nov 2023
Application note Clocking for Medical Ultrasound Systems (Rev. A) PDF | HTML 30 Sep 2020

Design & development

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Evaluation board

LMK00301EVAL — LMK00301 Evaluation Board

The LMK00301 Evaluation Board allows functional and performance verification of the LMK00301 high-performance 1:10 differential fanout buffer device.

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LMK00301 IBIS Model (Rev. B)

SNAM031B.ZIP (118 KB) - IBIS Model
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WQFN (RHS) 48 Ultra Librarian
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