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Product details

Parameters

Function Fanout Additive RMS jitter (Typ) (fs) 51 Output frequency (Max) (MHz) 3100 Number of outputs 11 Output supply voltage (V) 3.3, 2.5 Core supply voltage (V) 3.3 Output skew (ps) 50 Features Pin programmable Operating temperature range (C) -40 to 85 Rating Catalog Output type HCSL, LVDS, LVPECL Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL open-in-new Find other Clock buffers

Package | Pins | Size

WQFN (RHS) 48 49 mm² 7 x 7 open-in-new Find other Clock buffers

Features

  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 3.1 GHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts 10 to 40 MHz Crystal or Single-Ended Clock
  • Two Banks With 5 Differential Outputs Each
    • LVPECL, LVDS, HCSL, or Hi-Z (Selectable Per Bank)
    • LVPECL Additive Jitter with LMK03806 Clock Source at 156.25 MHz:
      • 20 fs RMS (10 kHz to 1 MHz)
      • 51 fs RMS (12 kHz to 20 MHz)
  • High PSRR: -65/-76 dBc (LVPECL/LVDS) at 156.25 MHz
  • LVCMOS Output with Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
  • Industrial Temperature Range: -40°C to +85°C

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Description

The LMK00301 is a 3-GHz, 10-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 5 differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00301 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies.

The LMK00301 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

The LMK00301A is nearly identical to the LMK00301, but does not have power supply sequencing requirements between the core and output supply domains.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 3
Type Title Date
* Datasheet LMK00301 3-GHz 10-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator datasheet (Rev. I) Dec. 04, 2017
Application notes Clocking for Medical Ultrasound Systems (Rev. A) Sep. 30, 2020
User guides LMK00301 Evaluation Board User Guide Jan. 27, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
299
Description

The LMK00301 Evaluation Board allows functional and performance verification of the LMK00301 high-performance 1:10 differential fanout buffer device.

Features

Features:

  • Low-noise clock fan-out via two banks of five differential outputs and one LVCMOS output
  • Selectable differential output type (LVPECL, LVDS, HCSL, or Hi-Z), selectable per bank via control pins
  • 3:1 input multiplexer with two universal input buffers and one crystal oscillator interface (...)

Software development

APPLICATION SOFTWARE & FRAMEWORKS Download
Clock Design Tool - Loop Filter & Device Configuration + Simulation
CLOCKDESIGNTOOL The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

Design tools & simulation

SIMULATION MODELS Download
SNAM031B.ZIP (118 KB) - IBIS Model
SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
WQFN (RHS) 48 View options

Ordering & quality

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