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LMK00301

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3-GHz, 10-output differential fanout buffer / level translator

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Data sheet

LMK00301

ACTIVE
Data sheet Order now

Product details

Function Fanout, Level translator Additive RMS jitter (typ) (fs) 51 Output frequency (max) (MHz) 3100 Number of outputs 11 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features Pin programmable Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVDS, LVPECL Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL
Function Fanout, Level translator Additive RMS jitter (typ) (fs) 51 Output frequency (max) (MHz) 3100 Number of outputs 11 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features Pin programmable Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVDS, LVPECL Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL
WQFN (RHS) 48 49 mm² 7 x 7
  • 3:1 input multiplexer
    • Two universal inputs operate up to 3.1 ghz and accept lvpecl, lvds, cml, sstl, hstl, hcsl, or single-ended clocks
    • One crystal input accepts 10-mhz to 40-mhz crystal or single-ended clock
  • Two banks with five differential outputs each
    • LVPECL, LVDS, HCSL, or Hi-Z (selectable per bank)
    • LVPECL additive jitter with lmk03806 clock source at 156.25 MHz:
      • 20 fs RMS (10 kHz to 1 MHz)
      • 51 fs RMS (12 kHz to 20 MHz)
  • Frequency range:
    • LVPECL (DC to 3100 MHz)
    • LVDS (DC to 2100 MHz)
    • HCSL (DC to 800 MHz)
    • LVCMOS (DC to 250 MHz)
  • High PSRR: –65 dBc (LVPECL) and –76 dBc (LVDS) at 156.25 MHz
  • LVCMOS output with synchronous enable input
  • Pin-controlled configuration
  • V CC core supply: 3.3 V ± 5%
  • Three independent V CCO output supplies: 3.3 V or 2.5 V ± 5%
  • Industrial temperature range: –40°C to +85°C
  • 3:1 input multiplexer
    • Two universal inputs operate up to 3.1 ghz and accept lvpecl, lvds, cml, sstl, hstl, hcsl, or single-ended clocks
    • One crystal input accepts 10-mhz to 40-mhz crystal or single-ended clock
  • Two banks with five differential outputs each
    • LVPECL, LVDS, HCSL, or Hi-Z (selectable per bank)
    • LVPECL additive jitter with lmk03806 clock source at 156.25 MHz:
      • 20 fs RMS (10 kHz to 1 MHz)
      • 51 fs RMS (12 kHz to 20 MHz)
  • Frequency range:
    • LVPECL (DC to 3100 MHz)
    • LVDS (DC to 2100 MHz)
    • HCSL (DC to 800 MHz)
    • LVCMOS (DC to 250 MHz)
  • High PSRR: –65 dBc (LVPECL) and –76 dBc (LVDS) at 156.25 MHz
  • LVCMOS output with synchronous enable input
  • Pin-controlled configuration
  • V CC core supply: 3.3 V ± 5%
  • Three independent V CCO output supplies: 3.3 V or 2.5 V ± 5%
  • Industrial temperature range: –40°C to +85°C

The LMK00301 is a 3-GHz, 10-output differential fanout buffer intended for high-frequency, low-jitter clock and data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of five differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00301 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies.

The LMK00301 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system. The LMK00301 offers a design spin, the LMK00301A, that does not have power supply sequencing requirements between the core and output supply domains.

The LMK00301 is a 3-GHz, 10-output differential fanout buffer intended for high-frequency, low-jitter clock and data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of five differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00301 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies.

The LMK00301 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system. The LMK00301 offers a design spin, the LMK00301A, that does not have power supply sequencing requirements between the core and output supply domains.
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* Data sheet LMK00301 3-GHz 10-Output Ultra-Low Additive Jitter Differential Clock Buffer and Level Translator datasheet (Rev. J) PDF | HTML 12 May 2023
Application note Clocking for Medical Ultrasound Systems (Rev. A) PDF | HTML 30 Sep 2020
EVM User's guide LMK00301 Evaluation Board User Guide 27 Jan 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK00301EVAL — LMK00301 Evaluation Board

The LMK00301 Evaluation Board allows functional and performance verification of the LMK00301 high-performance 1:10 differential fanout buffer device.

User guide: PDF
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Support software

CLOCKDESIGNTOOL — Clock Design Tool Software

The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

Supported products & hardware

Supported products & hardware

Products
Clock generators
LMK02000 — 1 to 800-MHz, precision clock distributor with integrated PLL and 3 LVDS / 5 LVPECL outputs LMK02002 — 1 to 800-MHz, precision clock distributor with integrated PLL and 4 LVPECL outputs LMK03000 — 1185 to 1296-MHz, 800fs RMS jitter, precision clock conditioner with integrated VCO LMK03001 — 1470 to 1570-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO LMK03002 — 1566 to 1724-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO LMK03033 — 1843 to 2160-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO LMK03200 — Precision 0-delay clock conditioner with integrated VCO LMK03806 — Ultra-low jitter clock generator with 14 outputs
RF PLLs & synthesizers
LMX2430 — 3.0-GHz/0.8-GHz PLLatinum dual high frequency synthesizer for RF personal communications LMX2433 — 3.6-GHz/1.7-GHz PLLatinum dual high frequency synthesizer for RF personal communications LMX2434 — 5.0-GHz/2.5-GHz PLLatinum low power dual frequency synthesizer for RF personal communications LMX2485 — 500-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications LMX2485E — 50-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications LMX2485Q-Q1 — 500MHz to 3GHz automotive delta-sigma low power dual PLL LMX2486 — 1-GHz to 4.5-GHz delta-sigma low power dual PLL for RF personal communications LMX2487 — 1 to 6-GHz delta-sigma low power dual PLLatinum frequency synthesizer with 3.0-GHz integer PLL LMX2487E — 3-GHz to 7.5-GHz delta-sigma low power dual PLL for RF personal communications LMX2531 — High performance frequency synthesizer system with integrated VCO LMX2541 — Ultra-low noise PLLatinum frequency synthesizer with integrated VCO LMX2581 — 3.76-GHz wideband frequency synthesizer with integrated VCO
Clock jitter cleaners & synchronizers
LMK04000 — Precision clock conditioners low-noise clock jitter cleaner with cascaded PLLs LMK04001 — Low-noise jitter cleaner with 1430 to 1570-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04002 — Low-noise jitter cleaner with 1600 to 1750-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04010 — Low-noise jitter cleaner with 1185 to 1296-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04011 — Low-noise jitter cleaner with 1430 to 1570-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04031 — Low-noise jitter cleaner with 1430 to 1570-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04033 — Low-noise jitter cleaner with 1840 to 2160-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04100 — Precision clock conditioners clock jitter cleaner with cascaded PLLs LMK04101 — Jitter cleaner with integrated 1430 to 1570-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04102 — Jitter cleaner with integrated 1600 to 1750-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04110 — Jitter cleaner with integrated 1185 to 1296-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04111 — Jitter cleaner with integrated 1430 to 1570-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04131 — Jitter cleaner with integrated 1430 to 1570-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04133 — Jitter cleaner with integrated 1840 to 2160-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04208 — Ultra low-noise clock jitter cleaner with 6 programmable outputs LMK04228 — Ultra low-noise clock jitter cleaner with dual loop PLLs LMK04806 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.5-GHz VCO LMK04808 — Low-noise clock jitter cleaner with dual loop PLLs and integrated 2.9-GHz VCO LMK04816 — Three input low-noise clock jitter cleaner with dual loop PLLs LMK04826 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 1840 to1970-MHz VCO0 LMK04828 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0. LMK04906 — Ultra low noise clock jitter cleaner/multiplier with 6 programmable outputs
Clock buffers
LMK00301 — 3-GHz, 10-output differential fanout buffer / level translator LMK00304 — 3.1-GHz differential clock buffer/level translator with 4 configurable outputs LMK00306 — 3.1-GHz differential clock buffer/level translator with 6 configurable outputs LMK00308 — 3.1-GHz differential clock buffer/level translator with 8 configurable outputs LMK01000 — 1.6-GHz high performance clock buffer, divider, and distributor with 3 LVDS & 5 LVPECL outputs LMK01010 — 1.6-GHz high performance clock buffer, divider, and distributor with 8 LVDS outputs LMK01020 — 1.6-GHz high performance clock buffer, divider, and distributor with 8 LVPECL outputs LMK01801 — Dual clock distribution
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Simulation model

LMK00301 IBIS Model (Rev. B)

SNAM031B.ZIP (118 KB) - IBIS Model
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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WQFN (RHS) 48 View options
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