SNAS512I September 2011 – December 2017 LMK00301

PRODUCTION DATA.

- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information

- RHS|48

- RHS|48

For the LMK00301, when powering the Vcc and Vcco pins from separate supply rails, it is recommended for the supplies to reach their regulation point at approximately the same time while ramping up, or reach ground potential at the same time while ramping down. Using simultaneous or ratiometric power supply sequencing prevents internal current flow from Vcc to Vcco pins that could occur when Vcc is powered before Vcco.

For the LMK00301A, there is no power supply sequencing requirement between Vcc and Vcco.

The current consumption values specified in *Electrical Characteristics* can be used to calculate the total power dissipation and IC power dissipation for any device configuration. The total V_{CC} core supply current (I_{CC_TOTAL}) can be calculated using Equation 5:

Equation 5. **I**_{CC_TOTAL} = I_{CC_CORE} + I_{CC_BANK_A} + I_{CC_BANK_B} + I_{CC_CMOS}

where

- I
_{CC_CORE}is the current for core logic and input blocks and depends on selected input (CLKinX or OSCin). - I
_{CC_BANK_A}is the current for Bank A and depends on output type (I_{CC_PECL}, I_{CC_LVDS}, I_{CC_HCSL}, or 0 mA if disabled). - I
_{CC_BANK_B}is the current for Bank B and depends on output type (I_{CC_PECL}, I_{CC_LVDS}, I_{CC_HCSL}, or 0 mA if disabled). - I
_{CC_CMOS}is the current for the LVCMOS output (or 0 mA if REFout is disabled).

Since the output supplies (V_{CCOA}, V_{CCOB}, V_{CCOC}) can be powered from 3 independent voltages, the respective output supply currents (I_{CCO_BANK_A}, I_{CCO_BANK_B}, I_{CCO_CMOS}) should be calculated separately.

I_{CCO_BANK} for either Bank A or B can be directly taken from the corresponding output supply current specification (I_{CCO_PECL}, I_{CCO_LVDS}, or I_{CCO_HCSL}) **provided the output loading matches the specified conditions**. Otherwise, I_{CCO_BANK} should be calculated as follows:

Equation 6. I_{CCO_BANK} = I_{BANK_BIAS} + (N * I_{OUT_LOAD})

where

- I
_{BANK_BIAS}is the output bank bias current (fixed value). - I
_{OUT_LOAD}is the DC load current per loaded output pair. - N is the number of loaded output pairs in the bank (N = 0 to 5).

Table 6 shows the typical I_{BANK_BIAS} values and I_{OUT_LOAD} expressions for the 3 differential output types.

For LVPECL, it is possible to use a larger termination resistor (R_{T}) to ground instead of terminating with 50 Ω to V_{TT} = Vcco - 2 V; this technique is commonly used to eliminate the extra termination voltage supply (V_{TT}) and potentially reduce device power dissipation at the expense of lower output swing. For example, when Vcco is 3.3 V, a R_{T} value of 160 Ω to ground will eliminate the 1.3 V termination supply without sacrificing much output swing. In this case, the typical I_{OUT_LOAD} is 25 mA, so I_{CCO_PECL} for a fully-loaded bank reduces to 158 mA (vs. 165 mA with 50 Ω resistors to Vcco - 2 V).

CURRENT PARAMETER |
LVPECL |
LVDS |
HCSL |
---|---|---|---|

I_{BANK_BIAS} |
33 mA | 34 mA | 6 mA |

I_{OUT_LOAD} |
(V_{OH} - V_{TT})/R_{T} + (V_{OL} - V_{TT})/R_{T} |
0 mA (No DC load current) | V_{OH}/R_{T} |

Once the current consumption is calculated or known for each supply, the total power dissipation (P_{TOTAL}) can be calculated as:

Equation 7. ** P**_{TOTAL} = (V_{CC}*I_{CC_TOTAL}) + (V_{CCOA}*I_{CCO_BANK_A}) + (V_{CCOB}*I_{CCO_BANK_B}) + (V_{CCOC}*I_{CCO_CMOS})

If the device configuration has LVPECL or HCSL outputs, then it is also necessary to calculate the power dissipated in any termination resistors (P_{RT_ PECL} and P_{RT_HCSL}) and in any termination voltages (P_{VTT}). The external power dissipation values can be calculated as follows:

Equation 8. **P**_{RT_PECL} (per LVPECL pair) = (V_{OH} - V_{TT})^{2}/R_{T} + (V_{OL} - V_{TT})^{2}/R_{T}

Equation 9. ** P**_{VTT_PECL} (per LVPECL pair) = V_{TT} * [(V_{OH} - V_{TT})/R_{T} + (V_{OL} - V_{TT})/R_{T}]

Equation 10. **P**_{RT_HCSL} (per HCSL pair) = V_{OH}^{2} / R_{T}

Finally, the IC power dissipation (P_{DEVICE}) can be computed by subtracting the external power dissipation values from P_{TOTAL} as follows:

Equation 11. **P**_{DEVICE} = P_{TOTAL} - N_{1}*(P_{RT_PECL} + P_{VTT_PECL}) - N_{2}*P_{RT_HCSL}

where

- N
_{1}is the number of LVPECL output pairs with termination resistors to V_{TT}(usually Vcco - 2 V or GND). - N
_{2}is the number of HCSL output pairs with termination resistors to GND.

This example shows how to calculate IC power dissipation for a configuration with separate V_{CC} and V_{CCO} supplies and unused outputs. Because some outputs are not used, the I_{CCO_PECL} value specified in *Electrical Characteristics* cannot be used directly, and output bank current (I_{CCO_BANK}) should be calculated to accurately estimate the IC power dissipation.

- V
_{CC}= 3.3 V, V_{CCOA}= 3.3 V, V_{CCOB}= 2.5 V. Typical I_{CC}and I_{CCO}values. - CLKin0/CLKin0* input is selected.
- Bank A is configured for LVPECL: 4 pairs used with R
_{T}= 50 Ω to V_{T}= Vcco - 2 V (1 pair unused). - Bank B is configured for LVDS: 3 pairs used with R
_{L}= 100 Ω differential (2 pairs unused). - REFout is disabled.
- T
_{A}= 85 °C

Using the current and power calculations from the previous section, we can compute P_{TOTAL} and P_{DEVICE}.

- From Equation 5: I
_{CC_TOTAL}= 8.5 mA + 20 mA + 26 mA + 0 mA = 54.5 mA - From Table 6: I
_{OUT_LOAD}(LVPECL) = (1.6 V - 0.5 V)/50 Ω + (0.75 V - 0.5 V)/50 Ω = 27 mA - From Equation 6: I
_{CCO_BANK_A}= 33 mA + (4 * 27 mA) = 141 mA - From Equation 7: P
_{TOTAL}= (3.3 V * 54.5 mA) + (3.3 V * 141 mA) + (2.5 V * 34 mA)] = 730 mW - From Equation 8: P
_{RT_PECL}= ((2.4 V - 1.3 V)^{2}/50 Ω) + ((1.55 V - 1.3 V)^{2}/50 Ω) = 25.5 mW (per output pair) - From Equation 9: P
_{VTT_PECL}= 0.5 V * [ ((2.4 V - 1.3 V) / 50 Ω) + ((1.55 V - 1.3 V) / 50 Ω) ] = 13.5 mW (per output pair) - From Equation 10: P
_{RT_HCSL}= 0 mW (no HCSL outputs) - From Equation 11: P
_{DEVICE}= 730 mW - (4 * (25.5 mW + 13.5 mW)) - 0 mW = 574 mW

In this example, the IC device will dissipate about 574 mW or 79% of the total power (730 mW), while the remaining 21% will be dissipated in the emitter resistors (102 mW for 4 pairs) and termination voltage (54 mW into Vcco - 2 V).

Based on the thermal resistance junction-to-case (R_{θJA}) of 28.5 °C/W, the estimated die junction temperature would be about 16.4 °C above ambient, or 101.4 °C when T_{A} = 85 °C.

This example shows how to calculate IC power dissipation for a configuration to estimate **worst-case power dissipation**. In this case, the maximum supply voltage and supply current values specified in *Electrical Characteristics* are used.

- Max V
_{CC}= V_{CCO}= 3.465 V. Max I_{CC}and I_{CCO}values. - CLKin0/CLKin0* input is selected.
- Banks A and B are configured for LVPECL: all outputs terminated with 50 Ω to V
_{T}= Vcco - 2 V. - REFout is enabled with 5 pF load.
- T
_{A}= 85 °C

Using the *maximum* supply current and power calculations from the previous section, we can compute P_{TOTAL} and P_{DEVICE}.

- From Equation 5: I
_{CC_TOTAL}= 10.5 mA + 27 mA + 27 mA + 5.5 mA = 70 mA - From I
_{CCO_PECL}max spec: I_{CCO_BANK_A}= I_{CCO_BANK_B}= 197 mA - From Equation 7: P
_{TOTAL}= 3.465 V * (70 mA + 197 mA + 197 mA + 10 mA) = 1642.4 mW - From Equation 8: P
_{RT_PECL}= ((2.57 V - 1.47 V)^{2}/50 Ω) + ((1.72 V - 1.47 V)^{2}/50 Ω) = 25.5 mW (per output pair) - From Equation 9: P
_{VTT_PECL}= 1.47 V * [ ((2.57 V - 1.47 V) / 50 Ω) + ((1.72 V - 1.47 V) / 50 Ω) ] = 39.5 mW (per output pair) - From Equation 10: P
_{RT_HCSL}= 0 mW (no HCSL outputs) - From Equation 11: P
_{DEVICE}= 1642.4 mW - (10 * (25.5 mW + 39.5 mW)) - 0 mW = 992.4 mW

In this worst-case example, the IC device will dissipate about 992.4 mW or 60% of the total power (1642.4 mW), while the remaining 40% will be dissipated in the LVPECL emitter resistors (255 mW for 10 pairs) and termination voltage (395 mW into Vcco - 2 V).

Based on θ_{JA} of 28.5 °C/W, the estimated die junction temperature would be about 28.3 °C above ambient, or 113.3 °C when T_{A} = 85 °C.

The Vcc and Vcco power supplies should have a high-frequency bypass capacitor, such as 0.1 uF or 0.01 uF, placed very close to each supply pin. 1 uF to 10 uF decoupling capacitors should also be placed nearby the device between the supply and ground planes. All bypass and decoupling capacitors should have short connections to the supply and ground plane through a short trace or via to minimize series inductance.

In practical system applications, power supply noise (ripple) can be generated from switching power supplies, digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00301, it can produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the single-side band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in dBc).

For the LMK00301, power supply ripple rejection, or PSRR, was measured as the single-sideband phase spur level (in dBc) modulated onto the clock output when a ripple signal was injected onto the Vcco supply. The PSRR test setup is shown in Figure 39.

A signal generator was used to inject a sinusoidal signal onto the Vcco supply of the DUT board, and the peak-to-peak ripple amplitude was measured at the Vcco pins of the device. A limiting amplifier was used to remove amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise analyzer. The phase spur level measurements were taken for clock frequencies of 156.25 MHz and 312.5 MHz under the following power supply ripple conditions:

- Ripple amplitude: 100 mVpp on Vcco = 2.5 V
- Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz

Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows:

Equation 12. DJ (ps pk-pk) = [(2*10^{(PSRR / 20)}) / (π*f_{CLK})] * 10^{12}

The “PSRR vs. Ripple Frequency” plots in *Typical Characteristics* show the ripple-induced phase spur levels for the differential output types at 156.25 MHz and 312.5 MHz . The LMK00301 exhibits very good and well-behaved PSRR characteristics across the ripple frequency range for all differential output types. The phase spur levels for LVPECL are below -64 dBc at 156.25 MHz and below -62 dBc at 312.5 MHz. Using Equation 12, these phase spur levels translate to Deterministic Jitter values of 2.57 ps pk-pk at 156.25 MHz and 1.62 ps pk-pk at 312.5 MHz. Testing has shown that the PSRR performance of the device improves for Vcco = 3.3 V under the same ripple amplitude and frequency conditions.

Power dissipation in the LMK00301 device can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is, as an estimate, T_{A} (ambient temperature) plus device power dissipation times R_{ θJA} should not exceed 125 °C.

The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to the printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.

A recommended land and via pattern is shown in Figure 40. More information on soldering WQFN packages can be obtained at: http://www.ti.com/packaging.

To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 40 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated.