SNAS642A June 2014 – July 2014 LMK00804B
The LMK00804B is a low skew, high performance clock fanout buffer which can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or de-asserted. The outputs are held in logic low state when the clock is disabled. A separate output enable terminal controls whether the outputs are active state or high-impedance state. The low additive jitter and phase noise floor, and guaranteed output and part-to-part skew characteristics make the LMK00804B ideal for applications demanding high performance and repeatability.
See also Device Comparison Table for descriptions of CDCLVC1310 and LMK00725 parts.
|PART NUMBER||PACKAGE||BODY SIZE (NOM)|
|LMK00804B||TSSOP (16)||5.00 mm × 4.40 mm|