LMK00804B Low Skew, 1-to-4 Multiplexed Differential/LVCMOS-to-LVCMOS/TTL Fanout Buffer | TI.com

LMK00804B
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
Low Skew, 1-to-4 Multiplexed Differential/LVCMOS-to-LVCMOS/TTL Fanout Buffer

 

Recommended alternative parts

  • LMK00101  -  10 Output Universal LVCMOS Buffer with Glitch-free Output-enable
  • CDCLVC1310  -  10 Output Universal LVCMOS Buffer with Glitch-free Output-enable
  • LMK00725  -  5 Output Universal LVPECL Buffer with Glitch-free Output-enable

Description

The LMK00804B is a low skew, high performance clock fanout buffer which can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or de-asserted. The outputs are held in logic low state when the clock is disabled. A separate output enable terminal controls whether the outputs are active state or high-impedance state. The low additive jitter and phase noise floor, and guaranteed output and part-to-part skew characteristics make the LMK00804B ideal for applications demanding high performance and repeatability.

See also Device Comparison Table for descriptions of CDCLVC1310 and LMK00725 parts.

Features

  • Four LVCMOS/LVTTL Outputs with 7 Ω Output
    Impedance
    • Additive Jitter: 0.04 ps RMS (typ) @ 125 MHz
    • Noise Floor: –166 dBc/Hz (typ) @ 125 MHz
    • Output Frequency: 350 MHz (max)
    • Output Skew: 35 ps (max)
    • Part-to-Part Skew: 700 ps (max)
  • Two Selectable Inputs
    • CLK, nCLK Pair Accepts LVPECL, LVDS,
      HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL
    • LVCMOS_CLK Accepts LVCMOS/LVTTL
  • Synchronous Clock Enable
  • Core/Output Power Supplies:
    • 3.3 V/3.3 V
    • 3.3 V/2.5 V
    • 3.3 V/1.8 V
    • 3.3 V/1.5 V
  • Package: 16-Lead TSSOP
  • Industrial Temperature Range: –40ºC to +85ºC

Design with LMK00804B

Frequency Number of Outputs
 MHz
Output Format

Parametrics

Compare all products in Clock buffers Email Download to Excel
Part number Order Function Additive RMS jitter (Typ) (fs) Output frequency (Max) (MHz) Number of outputs VCC out (V) VCC core (V) Features Operating temperature range (C) Rating Output type Package Group Package size: mm2:W x L (PKG) Input type
LMK00804B Order now Single-ended     40     350     4     3.3
2.5
1.8
1.5    
3.3       -40 to 85     Catalog     LVCMOS
LVTTL    
TSSOP | 16     16TSSOP: 22 mm2: 4.4 x 5 (TSSOP | 16)     HCSL
LVCMOS
LVDS
LVPECL
LVTTL    
CDCLVC1102 Order now Single-ended     70     250     2     2.5
3.3    
2.5
3.3    
  -40 to 85     Catalog     LVCMOS     TSSOP | 8     8TSSOP: 19 mm2: 6.4 x 3 (TSSOP | 8)     LVCMOS    
CDCLVC1103 Order now Single-ended     70     250     3     2.5
3.3    
2.5
3.3    
  -40 to 85     Catalog     LVCMOS     TSSOP | 8     8TSSOP: 19 mm2: 6.4 x 3 (TSSOP | 8)     LVCMOS    
CDCLVC1104 Order now Single-ended     70     250     4     2.5
3.3    
2.5
3.3    
  -40 to 85     Catalog     LVCMOS     TSSOP | 8     8TSSOP: 19 mm2: 6.4 x 3 (TSSOP | 8)     LVCMOS    
CDCLVC1106 Order now Single-ended     70     250     6     2.5
3.3    
2.5
3.3    
  -40 to 85     Catalog     LVCMOS     TSSOP | 14     14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)     LVCMOS    
CDCLVC1108 Order now Single-ended     70     250     8     2.5
3.3    
2.5
3.3    
  -40 to 85     Catalog     LVCMOS     TSSOP | 16     16TSSOP: 22 mm2: 4.4 x 5 (TSSOP | 16)     LVCMOS    
CDCLVC1110 Order now Single-ended     70     250     10     2.5
3.3    
2.5
3.3    
  -40 to 85     Catalog     LVCMOS     TSSOP | 20     20TSSOP: 42 mm2: 6.4 x 6.5 (TSSOP | 20)     LVCMOS    
CDCLVC1112 Order now Single-ended     70