Product details

Function Level translator, Single-ended Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 350 Number of outputs 4 Output supply voltage (V) 1.5, 1.8, 2.5, 3.3 Core supply voltage (V) 3.3 Output skew (ps) 35 Features Level translation, Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS, LVTTL Input type HCSL, LVCMOS, LVDS, LVPECL, LVTTL
Function Level translator, Single-ended Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 350 Number of outputs 4 Output supply voltage (V) 1.5, 1.8, 2.5, 3.3 Core supply voltage (V) 3.3 Output skew (ps) 35 Features Level translation, Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS, LVTTL Input type HCSL, LVCMOS, LVDS, LVPECL, LVTTL
TSSOP (PW) 16 32 mm² 5 x 6.4
  • Four LVCMOS/LVTTL Outputs with 7 Ω Output
    Impedance
    • Additive Jitter: 0.04 ps RMS (typ) @ 125 MHz
    • Noise Floor: –166 dBc/Hz (typ) @ 125 MHz
    • Output Frequency: 350 MHz (max)
    • Output Skew: 35 ps (max)
    • Part-to-Part Skew: 700 ps (max)
  • Two Selectable Inputs
    • CLK, nCLK Pair Accepts LVPECL, LVDS,
      HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL
    • LVCMOS_CLK Accepts LVCMOS/LVTTL
  • Synchronous Clock Enable
  • Core/Output Power Supplies:
    • 3.3 V/3.3 V
    • 3.3 V/2.5 V
    • 3.3 V/1.8 V
    • 3.3 V/1.5 V
  • Package: 16-Lead TSSOP
  • Industrial Temperature Range: –40ºC to +85ºC
  • Four LVCMOS/LVTTL Outputs with 7 Ω Output
    Impedance
    • Additive Jitter: 0.04 ps RMS (typ) @ 125 MHz
    • Noise Floor: –166 dBc/Hz (typ) @ 125 MHz
    • Output Frequency: 350 MHz (max)
    • Output Skew: 35 ps (max)
    • Part-to-Part Skew: 700 ps (max)
  • Two Selectable Inputs
    • CLK, nCLK Pair Accepts LVPECL, LVDS,
      HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL
    • LVCMOS_CLK Accepts LVCMOS/LVTTL
  • Synchronous Clock Enable
  • Core/Output Power Supplies:
    • 3.3 V/3.3 V
    • 3.3 V/2.5 V
    • 3.3 V/1.8 V
    • 3.3 V/1.5 V
  • Package: 16-Lead TSSOP
  • Industrial Temperature Range: –40ºC to +85ºC

The LMK00804B is a low skew, high performance clock fanout buffer which can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or de-asserted. The outputs are held in logic low state when the clock is disabled. A separate output enable terminal controls whether the outputs are active state or high-impedance state. The low additive jitter and phase noise floor, and guaranteed output and part-to-part skew characteristics make the LMK00804B ideal for applications demanding high performance and repeatability.

See also Device Comparison Table for descriptions of CDCLVC1310 and LMK00725 parts.

The LMK00804B is a low skew, high performance clock fanout buffer which can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or de-asserted. The outputs are held in logic low state when the clock is disabled. A separate output enable terminal controls whether the outputs are active state or high-impedance state. The low additive jitter and phase noise floor, and guaranteed output and part-to-part skew characteristics make the LMK00804B ideal for applications demanding high performance and repeatability.

See also Device Comparison Table for descriptions of CDCLVC1310 and LMK00725 parts.

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Technical documentation

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Type Title Date
* Data sheet LMK00804B Low Skew, 1-to-4 Multiplexed Differential/LVCMOS-to-LVCMOS/TTL Fanout Buffer datasheet (Rev. A) PDF | HTML 07 Jul 2014
EVM User's guide LMK00804BEVM User’s Guide 27 Jun 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK00804B-Q1EVM — 4-output low-jitter differential/LVCMOS-to-LVCMOS fan-out buffer evaluation board

The LMK00804B-Q1 is a low skew, high performance clock fan-out buffer, which distributes up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels).  The clocks are derived from one of two selectable inputs, which can accept differential or single-ended input signals. The (...)
User guide: PDF
Not available on TI.com
Evaluation board

LMK00804BEVM — LMK00804BEVM 4-Output Low-Jitter Differential/LVCMOS-to-LVCMOS Fanout Buffer Evaluation Board

The LMK00804B is a low skew, high performance clock fanout buffer, which distributes up to four LVCMOS/LVTTL outputs (3.3V, 2.5V, 1.8V, or 1.5V levels).  The clocks are derived from one of two selectable inputs, which can accept differential or single-ended input signals. This evaluation (...)

User guide: PDF
Not available on TI.com
Evaluation board

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The MMWCAS-RF evaluation module (EVM) is a sensing solution from TI implementing a four-device cascaded array of AWR1243 or AWR2243 devices. In this cascaded radar configuration, a single master device distributes a 20-GHz local-oscillator (LO) signal between all four devices, allowing these four (...)
User guide: PDF | HTML
Not available on TI.com
Simulation model

LMK00804B IBIS Model (Rev. A)

SNAM166A.ZIP (55 KB) - IBIS Model
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-01056 — 20-bit 1MSPS DAQ Reference Design Optimizing Power Supply Efficiency While Minimizing EMI

This reference design for high performance data acquisition (DAQ) systems optimizes power stage in order to reduce power consumption and minimize the effect of EMI from switching regulator by using LMS3635-Q1 buck converter.  This reference designs yields 7.2% efficiency improvement at most (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01054 — Multi-Rail Power Reference Design for Eliminating EMI Effects in High Performance DAQ Systems

The TIDA-01054 reference design helps eliminate the performance degrading effects of EMI on Data Acquisition (DAQ) systems greater than 16 bits with the help of the LM53635 buck converter. The buck converter enables the designer to place power solutions close to the signal path without the (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01013 — Low Power, Low Noise 24b Analog Front-End Reference Design for DAQ and Wireless Sensor IoT Systems

The need for lower power, lower noise analog front-ends (AFE) is becoming increasingly important in many applications today, such as data acquisition systems (DAQs), field instrumentation, Internet-of-Things (IoT), and automatic test equipment. In many cases, this need is highlighted by the advent (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01055 — ADC Voltage Reference Buffer Optimization Reference Design for High Performance DAQ Systems

The TIDA-01055 reference design for high performance DAQ Systems optimizes the ADC reference buffer to improve SNR performance and reduce power consumption with the TI OPA837 high-speed op amp. This device is used in a composite buffer configuration and provides a 22% power improvement over (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01057 — Reference Design Maximizing Signal Dynamic Range for True 10 Vpp Differential Input to 20 bit ADC

This reference design is designed for high performance data acquisition(DAQ) systems to improve the dynamic range of 20 bit differential input ADCs. Many DAQ systems require the measurement capability at a wide FSR (Full Scale Range) in order to obtain sufficient signal dynamic range. Many earlier (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01051 — Reference Design Optimizing FPGA Utilization and Data Throughput for Automatic Test Equipment

The TIDA-01051 reference design is used to demonstrate optimized channel density, integration, power consumption, clock distribution and signal chain performance of very high channel count data acquisition (DAQ) systems such as those used in automatic test equipment (ATE). Using serializers, such (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01050 — Optimized Analog Front End DAQ System Reference Design for 18 bit SAR Data Converters

The TIDA-01050 reference design aims to improve the integration, power consumption, performance, and clocking issues typically associated with automatic test equipment. This design is applicable to any ATE system but most applicable to systems requiring a large number of input channels.
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01052 — ADC Driver Reference Design Improving Full Scale THD Using Negative Supply

The TIDA-01052 reference design aims to highlight system performance increases seen using a negative voltage rail on the analog front end driver amplifiers rather than ground. This concept is relative to all analog front ends, however this design is aimed specifically at automatic test equipment.
Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 16 Ultra Librarian

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