SNAS642A June   2014  – July 2014 LMK00804B

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Pin Characteristics
    2. 7.2  Absolute Maximum Ratings
    3. 7.3  Handling Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Power Supply Characteristics
    7. 7.7  LVCMOS / LVTTL DC Characteristics
    8. 7.8  Differential Input DC Characteristics
    9. 7.9  Electrical Characteristics (VDDO = 3.3 V ± 5%)
    10. 7.10 Electrical Characteristics (VDDO = 2.5 V ± 5%)
    11. 7.11 Electrical Characteristics (VDDO = 1.8 V ± 0.15 V)
    12. 7.12 Electrical Characteristics (VDDO = 1.5 V ± 5%)
    13. 7.13 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
      1. 9.2.1 25
    3. 9.3 Feature Description
      1. 9.3.1 Clock Enable Timing
    4. 9.4 Device Functional Modes
      1. 9.4.1 Clock Input Function
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Output Clock Interface Circuit
    3. 10.3 Input Detail
    4. 10.4 Input Clock Interface Circuits
    5. 10.5 Typical Applications
      1. 10.5.1 Design Requirements
      2. 10.5.2 Detailed Design Procedure
      3. 10.5.3 Application Curves
        1. 10.5.3.1 System-Level Phase Noise and Additive Jitter Measurement
    6. 10.6 Do's and Don'ts
      1. 10.6.1 Power Considerations
      2. 10.6.2 Recommendations for Unused Input and Output Pins
      3. 10.6.3 Input Slew Rate Considerations
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Considerations
      1. 11.1.1 Power-Supply Filtering
      2. 11.1.2 Thermal Management
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ground Planes
      2. 12.1.2 Power Supply Pins
      3. 12.1.3 Differential Input Termination
      4. 12.1.4 LVCMOS Input Termination
      5. 12.1.5 Output Termination
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

12.1.1 Ground Planes

Solid ground planes are recommended as they provide a low-impedance return paths between the device and its bypass capacitors and its clock source and destination devices.

Avoid return paths of other system circuitry (for example, high-speed/digital logic, switching power supplies, and so forth) from passing through the local ground of the device to minimize noise coupling, which could induce added jitter and spurious noise.

12.1.2 Power Supply Pins

Follow the power supply schematic and layout example described in Power-Supply Filtering.

12.1.3 Differential Input Termination

  • Place input termination or biasing resistors as close as possible to the CLK/nCLK pins.
  • Avoid or minimize vias in the 50 Ω input traces to minimize impedance discontinuities. Intra-pair skew should be also be minimized on the differential input traces.
  • If not used, CLK/nCLK inputs may be left floating.

12.1.4 LVCMOS Input Termination

  • When the LVCMOS_CLK input is driven from a LVCMOS driver that is series terminated to match the characteristic impedance of the trace, then input termination is not necessary; otherwise, place the input termination resistor as close as possible to the LVCMOS_CLK input.
  • Avoid or minimize vias in the 50 Ω input trace to minimize impedance discontinuities.
  • If not used, LVCMOS_CLK input may be left floating.

12.1.5 Output Termination

  • Place 43 Ω series termination resistors as close as possible to the Qx outputs at the launch of the 50 Ω traces.
  • Avoid or minimize vias in the 50 Ω input traces to minimize impedance discontinuities.
  • If not used, any Qx output should be left floating and not routed.

12.2 Layout Example

Please refer to the LMK00804BEVM for a layout example. A sample PCB layer is shown below.

PCB_LayerPlots_1to1_Page_1_LMK00804EVM_v2.pngFigure 21. Sample PCB Layout, Layer 1 (Top View)