SNAS699B January   2017  – July 2019 LMK04610

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: LMK04610
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Digital Input and Output Characteristics (CLKin_SEL, STATUSx, SYNC, RESETN)
    6. 7.6  Clock Input Characteristics (CLKinX)
    7. 7.7  Clock Input Characteristics (OSCin)
    8. 7.8  PLL1 Specification Characteristics
    9. 7.9  PLL2 Specification Characteristics
    10. 7.10 Clock Output Type Characteristics (CLKoutX)
    11. 7.11 Oscillator Output Characteristics (OSCout)
    12. 7.12 Jitter and Phase Noise Characteristics for CLKoutX and OSCout
    13. 7.13 Clock Output Skew and Isolation Characteristics
    14. 7.14 Clock Output Delay Characteristics
    15. 7.15 DEFAULT POWER on RESET CLOCK OUTPUT Characteristics
    16. 7.16 Power Supply Characteristics
    17. 7.17 Typical Power Supply Noise Rejection Characteristics
    18. 7.18 SPI Interface Timing
    19. 7.19 Timing Diagram
    20. 7.20 Typical Characteristics
      1. 7.20.1 Clock Output AC Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
    2. 8.2 Output Termination Scheme
      1. 8.2.1 HSDS 4/6/8mA
      2. 8.2.2 HCSL
      3. 8.2.3 LVCMOS
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Jitter Cleaning
      2. 9.1.2 Two Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
      3. 9.1.3 VCXO Buffered Output
      4. 9.1.4 Frequency Holdover
      5. 9.1.5 Integrated Programmable PLL1 and PLL2 Loop Filter
      6. 9.1.6 Internal VCOs
      7. 9.1.7 Clock Distribution
        1. 9.1.7.1 Output Clock Divider
        2. 9.1.7.2 Output Clock Delay
        3. 9.1.7.3 Glitchless Half-Step and Glitchless Analog Delay
        4. 9.1.7.4 Programmable Output Formats
        5. 9.1.7.5 Clock Output SYNChronization
      8. 9.1.8 Status Pins
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
        1. 9.3.1.1 Input Clock Switching
          1. 9.3.1.1.1 Input Clock Switching – Register Select Mode
          2. 9.3.1.1.2 Input Clock Switching – Pin Select Mode (CLKin_SEL)
          3. 9.3.1.1.3 Input Clock Switching – Automatic Mode
        2. 9.3.1.2 Loss of Signal Detection – LOS
          1. 9.3.1.2.1 LOS – Assertion
          2. 9.3.1.2.2 LOS – Reference Clock Recovery
        3. 9.3.1.3 Driving CLKin and OSCin Inputs
          1. 9.3.1.3.1 Driving CLKin and OSCin Pins With a Differential Source
          2. 9.3.1.3.2 Driving CLKin and OSCin Pins With a Single-Ended Source
      2. 9.3.2 Clock Outputs (CLKoutX)
        1. 9.3.2.1 HCSL
        2. 9.3.2.2 HSDS
        3. 9.3.2.3 SYNC
        4. 9.3.2.4 Digital Delay
          1. 9.3.2.4.1 Fixed Digital Delay
          2. 9.3.2.4.2 Dynamic Digital Delay
        5. 9.3.2.5 Analog Delay
      3. 9.3.3 OSCout
        1. 9.3.3.1 Pin-Controlled OSCout Divider
      4. 9.3.4 STATUS0/1 and SYNC Pin Functions
        1. 9.3.4.1 Common STATUS0/1 and SYNC Pin Functions
        2. 9.3.4.2 Additional STATUS0 Pin Functions
        3. 9.3.4.3 Additional SYNC Pin Functions
      5. 9.3.5 PLL1 and PLL2
        1. 9.3.5.1 PLL1
          1. 9.3.5.1.1 PLL1 Proportional Modes
          2. 9.3.5.1.2 PLL1 Higher Order Poles
        2. 9.3.5.2 PLL2
          1. 9.3.5.2.1 PLL2 Divider
          2. 9.3.5.2.2 PLL2 Input Modes
          3. 9.3.5.2.3 PLL2 Loop Filter
          4. 9.3.5.2.4 PLL2 3rd Order Loop Filter
          5. 9.3.5.2.5 PLL2 Voltage Controlled Oscillator (VCO)
          6. 9.3.5.2.6 Examples of PLL2 Setting
        3. 9.3.5.3 Digital Lock Detect
          1. 9.3.5.3.1 Calculating Digital Lock Detect Frequency Accuracy
      6. 9.3.6 Holdover
        1. 9.3.6.1 Holdover Flowchart
        2. 9.3.6.2 Enable Holdover
          1. 9.3.6.2.1 Automatic Tracked CTRL_VCXO Holdover Mode
        3. 9.3.6.3 Enter Holdover
          1. 9.3.6.3.1 LOS_x Detect
          2. 9.3.6.3.2 PLL1 DLD Detect
          3. 9.3.6.3.3 CTRL_VCXO Rail Detect
            1. 9.3.6.3.3.1 Absolute Limits
            2. 9.3.6.3.3.2 Relative Limits
          4. 9.3.6.3.4 Manual Holdover Enable – Register Control
          5. 9.3.6.3.5 Manual Holdover Enable – Pin Control
          6. 9.3.6.3.6 Start-Up into Holdover
        4. 9.3.6.4 During Holdover
        5. 9.3.6.5 Exiting Holdover
        6. 9.3.6.6 Holdover Frequency Accuracy
        7. 9.3.6.7 Holdover Mode – Automatic Exit by LOS Deassertion
        8. 9.3.6.8 Holdover Mode – Automatic Exit of Holdover With Holdover Counter
      7. 9.3.7 JEDEC JESD204B
        1. 9.3.7.1 SYNC Pins
        2. 9.3.7.2 SYNC modes
        3. 9.3.7.3 SYSREF Modes
          1. 9.3.7.3.1 SYSREF Pulser
            1. 9.3.7.3.1.1 SPI Pulser Mode
            2. 9.3.7.3.1.2 Pin Pulser Mode
            3. 9.3.7.3.1.3 Multiple SYSREF Frequencies
          2. 9.3.7.3.2 Continuous SYSREF
          3. 9.3.7.3.3 SYSREF Request
        4. 9.3.7.4 How to Enable SYSREF
          1. 9.3.7.4.1 Setup Example 1: Pulser Mode, Pin Controlled
          2. 9.3.7.4.2 Setup Example 2: Pulser Mode, Spi Controlled
      8. 9.3.8 Zero Delay Mode (ZDM)
      9. 9.3.9 Power-Up Sequence
    4. 9.4 Device Functional Modes
      1. 9.4.1 Dual PLL
      2. 9.4.2 Single PLL
      3. 9.4.3 PLL2 Bypass
      4. 9.4.4 Clock Distribution
    5. 9.5 Programming
      1. 9.5.1 Recommended Programming Sequence
        1. 9.5.1.1 Readback
    6. 9.6 Register Maps
      1. 9.6.1 Register Map for Device Programming
      2. 9.6.2 Device Register Descriptions
        1. 9.6.2.1   CONFIGA
        2. 9.6.2.2   RESERVED1
        3. 9.6.2.3   RESERVED2
        4. 9.6.2.4   CHIP_TYPE
        5. 9.6.2.5   CHIP_ID_BY1
        6. 9.6.2.6   CHIP_ID_BY0
        7. 9.6.2.7   CHIP_VER
        8. 9.6.2.8   RESERVED3
        9. 9.6.2.9   RESERVED4
        10. 9.6.2.10  RESERVED5
        11. 9.6.2.11  RESERVED6
        12. 9.6.2.12  RESERVED7
        13. 9.6.2.13  VENDOR_ID_BY1
        14. 9.6.2.14  VENDOR_ID_BY0
        15. 9.6.2.15  RESERVED8
        16. 9.6.2.16  RESERVED9
        17. 9.6.2.17  STARTUP_CFG
        18. 9.6.2.18  STARTUP
        19. 9.6.2.19  DIGCLKCTRL
        20. 9.6.2.20  PLL2REFCLKDIV
        21. 9.6.2.21  GLBL_SYNC_SYSREF
        22. 9.6.2.22  CLKIN_CTRL0
        23. 9.6.2.23  CLKIN_CTRL1
        24. 9.6.2.24  CLKIN0CTRL
        25. 9.6.2.25  CLKIN1CTRL
        26. 9.6.2.26  CLKIN0RDIV_BY1
        27. 9.6.2.27  CLKIN0RDIV_BY0
        28. 9.6.2.28  CLKIN1RDIV_BY1
        29. 9.6.2.29  CLKIN1RDIV_BY0
        30. 9.6.2.30  CLKIN0LOS_REC_CNT
        31. 9.6.2.31  CLKIN0LOS_LAT_SEL
        32. 9.6.2.32  CLKIN1LOS_REC_CNT
        33. 9.6.2.33  CLKIN1LOS_LAT_SEL
        34. 9.6.2.34  CLKIN_SWCTRL0
        35. 9.6.2.35  CLKIN_SWCTRL1
        36. 9.6.2.36  CLKIN_SWCTRL2
        37. 9.6.2.37  OSCIN_CTRL
        38. 9.6.2.38  OSCOUT_CTRL
        39. 9.6.2.39  OSCOUT_DIV
        40. 9.6.2.40  OSCOUT_DRV
        41. 9.6.2.41  OUTCH_SWRST
        42. 9.6.2.42  OUTCH1CNTL0
        43. 9.6.2.43  OUTCH1CNTL1
        44. 9.6.2.44  OUTCH2CNTL0
        45. 9.6.2.45  OUTCH2CNTL1
        46. 9.6.2.46  OUTCH34CNTL0
        47. 9.6.2.47  OUTCH34CNTL1
        48. 9.6.2.48  OUTCH5CNTL0
        49. 9.6.2.49  OUTCH5CNTL1
        50. 9.6.2.50  OUTCH6CNTL0
        51. 9.6.2.51  OUTCH6CNTL1
        52. 9.6.2.52  OUTCH78CNTL0
        53. 9.6.2.53  OUTCH78CNTL1
        54. 9.6.2.54  OUTCH9CNTL0
        55. 9.6.2.55  OUTCH9CNTL1
        56. 9.6.2.56  OUTCH10CNTL0
        57. 9.6.2.57  OUTCH10CNTL1
        58. 9.6.2.58  OUTCH1DIV_BY1
        59. 9.6.2.59  OUTCH1DIV_BY0
        60. 9.6.2.60  OUTCH2DIV_BY1
        61. 9.6.2.61  OUTCH2DIV_BY0
        62. 9.6.2.62  OUTCH34DIV_BY1
        63. 9.6.2.63  OUTCH34DIV_BY0
        64. 9.6.2.64  OUTCH5DIV_BY1
        65. 9.6.2.65  OUTCH5DIV_BY0
        66. 9.6.2.66  OUTCH6DIV_BY1
        67. 9.6.2.67  OUTCH6DIV_BY0
        68. 9.6.2.68  OUTCH78DIV_BY1
        69. 9.6.2.69  OUTCH78DIV_BY0
        70. 9.6.2.70  OUTCH9DIV_BY1
        71. 9.6.2.71  OUTCH9DIV_BY0
        72. 9.6.2.72  OUTCH10DIV_BY1
        73. 9.6.2.73  OUTCH10DIV_BY0
        74. 9.6.2.74  OUTCH_DIV_INV
        75. 9.6.2.75  PLL1CTRL0
        76. 9.6.2.76  PLL1CTRL1
        77. 9.6.2.77  PLL1CTRL2
        78. 9.6.2.78  PLL1_SWRST
        79. 9.6.2.79  PLL1WNDWSIZE
        80. 9.6.2.80  PLL1STRCELL
        81. 9.6.2.81  PLL1CPSETTING
        82. 9.6.2.82  PLL1CPSETTING_FL
        83. 9.6.2.83  PLL1_HOLDOVER_CTRL1
        84. 9.6.2.84  PLL1_HOLDOVER_MAXCNT_BY3
        85. 9.6.2.85  PLL1_HOLDOVER_MAXCNT_BY2
        86. 9.6.2.86  PLL1_HOLDOVER_MAXCNT_BY1
        87. 9.6.2.87  PLL1_HOLDOVER_MAXCNT_BY0
        88. 9.6.2.88  PLL1_NDIV_BY1
        89. 9.6.2.89  PLL1_NDIV_BY0
        90. 9.6.2.90  PLL1_LOCKDET_CYC_CNT_BY2
        91. 9.6.2.91  PLL1_LOCKDET_CYC_CNT_BY1
        92. 9.6.2.92  PLL1_LOCKDET_CYC_CNT_BY0
        93. 9.6.2.93  PLL1_STRG_BY4
        94. 9.6.2.94  PLL1_STRG_BY3
        95. 9.6.2.95  PLL1_STRG_BY2
        96. 9.6.2.96  PLL1_STRG_BY1
        97. 9.6.2.97  PLL1_STRG_BY0
        98. 9.6.2.98  PLL1RCCLKDIV
        99. 9.6.2.99  PLL2_CTRL0
        100. 9.6.2.100 PLL2_CTRL1
        101. 9.6.2.101 PLL2_CTRL2
        102. 9.6.2.102 PLL2_SWRST
        103. 9.6.2.103 PLL2_LF_C4R4
        104. 9.6.2.104 PLL2_LF_C3R3
        105. 9.6.2.105 PLL2_CP_SETTING
        106. 9.6.2.106 PLL2_NDIV_BY1
        107. 9.6.2.107 PLL2_NDIV_BY0
        108. 9.6.2.108 PLL2_RDIV_BY1
        109. 9.6.2.109 PLL2_RDIV_BY0
        110. 9.6.2.110 PLL2_STRG_INIT_BY1
        111. 9.6.2.111 PLL2_STRG_INIT_BY0
        112. 9.6.2.112 RAILDET_UP
        113. 9.6.2.113 RAILDET_LOW
        114. 9.6.2.114 PLL2_AC_CTRL
        115. 9.6.2.115 PLL2_CURR_STOR_CELL
        116. 9.6.2.116 PLL2_AC_THRESHOLD
        117. 9.6.2.117 PLL2_AC_STRT_THRESHOLD
        118. 9.6.2.118 PLL2_AC_WAIT_CTRL
        119. 9.6.2.119 PLL2_AC_JUMPSTEP
        120. 9.6.2.120 PLL2_LD_WNDW_SIZE
        121. 9.6.2.121 PLL2_LD_WNDW_SIZE_INITIAL
        122. 9.6.2.122 PLL2_LOCKDET_CYC_CNT_BY2
        123. 9.6.2.123 PLL2_LOCKDET_CYC_CNT_BY1
        124. 9.6.2.124 PLL2_LOCKDET_CYC_CNT_BY0
        125. 9.6.2.125 PLL2_LOCKDET_CYC_CNT_INITIAL_BY2
        126. 9.6.2.126 PLL2_LOCKDET_CYC_CNT_INITIAL_BY1
        127. 9.6.2.127 PLL2_LOCKDET_CYC_CNT_INITIAL_BY0
        128. 9.6.2.128 IOCTRL_SPI0
        129. 9.6.2.129 IOCTRL_SPI1
        130. 9.6.2.130 IOTEST_SDIO
        131. 9.6.2.131 IOTEST_SCL
        132. 9.6.2.132 IOTEST_SCS
        133. 9.6.2.133 IOCTRL_STAT0
        134. 9.6.2.134 IOCTRL_STAT1
        135. 9.6.2.135 STAT1MUX
        136. 9.6.2.136 STAT0MUX
        137. 9.6.2.137 STATPLL2CLKDIV
        138. 9.6.2.138 IOTEST_STAT0
        139. 9.6.2.139 IOTEST_STAT1
        140. 9.6.2.140 IOCTRL_SYNC
        141. 9.6.2.141 DUMMY_REGISTER_1
        142. 9.6.2.142 IOCTRL_CLKINSEL1
        143. 9.6.2.143 IOTEST_CLKINSEL1
        144. 9.6.2.144 PLL1_TSTMODE
        145. 9.6.2.145 PLL2_CTRL
        146. 9.6.2.146 STATUS
        147. 9.6.2.147 PLL2_DLD_EN
        148. 9.6.2.148 PLL2_DUAL_LOOP
        149. 9.6.2.149 RESERVED10
        150. 9.6.2.150 CH1_DDLY_BY0
        151. 9.6.2.151 CH2_DDLY_BY0
        152. 9.6.2.152 CH34_DDLY_BY0
        153. 9.6.2.153 CH5_DDLY_BY0
        154. 9.6.2.154 CH6_DDLY_BY0
        155. 9.6.2.155 CH78_DDLY_BY0
        156. 9.6.2.156 CH9_DDLY_BY0
        157. 9.6.2.157 CH10_DDLY_BY0
        158. 9.6.2.158 OUTCH1_JESD_CTRL
        159. 9.6.2.159 OUTCH2_JESD_CTRL
        160. 9.6.2.160 OUTCH3_JESD_CTRL
        161. 9.6.2.161 OUTCH4_JESD_CTRL
        162. 9.6.2.162 OUTCH5_JESD_CTRL
        163. 9.6.2.163 OUTCH6_JESD_CTRL
        164. 9.6.2.164 OUTCH7_JESD_CTRL
        165. 9.6.2.165 OUTCH8_JESD_CTRL
        166. 9.6.2.166 OUTCH9_JESD_CTRL
        167. 9.6.2.167 OUTCH10_JESD_CTRL
        168. 9.6.2.168 CLKMUXVECTOR
        169. 9.6.2.169 OUTCH1CNTL2
        170. 9.6.2.170 OUTCH2CNTL2
        171. 9.6.2.171 OUTCH34CNTL2
        172. 9.6.2.172 OUTCH5CNTL2
        173. 9.6.2.173 OUTCH6CNTL2
        174. 9.6.2.174 OUTCH78CNTL2
        175. 9.6.2.175 OUTCH9CNTL2
        176. 9.6.2.176 OUTCH10CNTL2
        177. 9.6.2.177 OUTCH1_JESD_CTRL1
        178. 9.6.2.178 OUTCH2_JESD_CTRL1
        179. 9.6.2.179 OUTCH3_JESD_CTRL1
        180. 9.6.2.180 OUTCH4_JESD_CTRL1
        181. 9.6.2.181 OUTCH5_JESD_CTRL1
        182. 9.6.2.182 OUTCH6_JESD_CTRL1
        183. 9.6.2.183 OUTCH7_JESD_CTRL1
        184. 9.6.2.184 OUTCH8_JESD_CTRL1
        185. 9.6.2.185 OUTCH9_JESD_CTRL1
        186. 9.6.2.186 OUTCH10_JESD_CTRL1
        187. 9.6.2.187 SYSREF_PLS_CNT
        188. 9.6.2.188 SYNCMUX
        189. 9.6.2.189 IOTEST_SYNC
        190. 9.6.2.190 OUTCH_ZDM
        191. 9.6.2.191 PLL2_CTRL3
        192. 9.6.2.192 PLL1_HOLDOVER_CTRL0
        193. 9.6.2.193 IOCTRL_SYNC_1
        194. 9.6.2.194 OUTCH_TOP_JESD_CTRL
        195. 9.6.2.195 OUTCH_BOT_JESD_CTRL
        196. 9.6.2.196 OUTCH_JESD_CTRL1
        197. 9.6.2.197 PLL2_CTRL4
        198. 9.6.2.198 PLL2_CTRL5
        199. 9.6.2.199 PLL2_CTRL6
        200. 9.6.2.200 PLL2_CTRL7
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Digital Lock Detect Frequency Accuracy
        1. 10.1.1.1 Minimum Lock Time Calculation Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PLL Loop Filter Design
        2. 10.2.2.2 Clock Output Assignment
        3. 10.2.2.3 Calculation Using LCM
        4. 10.2.2.4 Device Programming
        5. 10.2.2.5 Device Selection
        6. 10.2.2.6 Clock Architect
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
      1. 10.3.1 Pin Connection Recommendations
  11. 11Power Supply Recommendations
    1. 11.1 Recommended Power Supply Connection
    2. 11.2 Current Consumption / Power Dissipation Calculations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 CLKin and OSCin
      2. 12.1.2 CLKout
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 Clock Design Tool
        2. 13.1.1.2 Clock Architect
        3. 13.1.1.3 TICS Pro
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.1 Register Map for Device Programming

Table 24 provides the register map for device programming. Any register can be read from the same data address it is written to.

Table 24. Register Map

ADDRESS DATA
[15:0] D7 D6 D5 D4 D3 D2 D1 D0
0x00 SWRST LSB_FIRST ADDR_ASCEND SDO_ACTIVE SDO_ACTIVE_CPY ADDR_ASCEND_CPY LSB_FIRST_CPY SWRST_CPY
0x01 RSRVD RSRVD1
0x02 RSRVD RSRVD2[1:0]
0x03 DEVID[1:0] RSRVD CHIPTYPE[3:0]
0x04 CHIPID[15:8]
0x05 CHIPID[7:0]
0x06 CHIPVER[7:0]
0x07 RSRVD RSRVD3
0x08 RSRVD RSRVD4
0x09 RSRVD RSRVD5
0x0A RSRVD RSRVD6
0x0B RSRVD RSRVD7
0x0C VENDORID[15:8]
0x0D VENDORID[7:0]
0x0E RSRVD RSRVD8
0x0F RSRVD RSRVD9
0x10 RSRVD OUTCH_MUTE CLKINBLK_LOSLDO_EN CH6TO10EN CH1TO5EN PLL2EN PLL1EN
0x11 RSRVD DEV_STARTUP
0x12 RSRVD DIG_CLK_EN PLL2_DIG_CLK_EN PORCLKAFTERLOCK
0x13 RSRVD PLL2_REF_DIGCLK_DIV[4:0]
0x14 EN_SYNC_PIN_FUNC RSRVD GLOBAL_CONT_SYSREF GLOBAL_SYSREF INV_SYNC_INPUT_SYNC_CLK SYNC_PIN_FUNC[1:0] GLOBAL_SYNC
0x15 RSRVD CLKIN_STAGGER_EN CLKIN_SWRST RSRVD CLKINSEL1_INV
0x16 CLKINBLK_ALL_EN CLKINSEL1_MODE[1:0] CLKINBLK_EN_BUF_CLK_PLL CLKINBLK_EN_BUF_BYP_PLL RSRVD RSRVD RSRVD
0x19 RSRVD CLKIN0_PLL1_INV CLKIN0_LOS_FRQ_DBL_EN CLKIN0_EN CLKIN0_SE_MODE CLKIN0_PRIO[2:0]
0x1A RSRVD CLKIN1_PLL1_INV CLKIN1_LOS_FRQ_DBL_EN CLKIN1_EN CLKIN1_SE_MODE CLKIN1_PRIO[2:0]
0x1F CLKIN0_PLL1_RDIV[15:8]
0x20 CLKIN0_PLL1_RDIV[7:0]
0x21 CLKIN1_PLL1_RDIV[15:8]
0x22 CLKIN1_PLL1_RDIV[7:0]
0x27 CLKIN0_LOS_REC_CNT[7:0]
0x28 CLKIN0_LOS_LAT_SEL[7:0]
0x29 CLKIN1_LOS_REC_CNT[7:0]
0x2A CLKIN1_LOS_LAT_SEL[7:0]
0x2B RSRVD SW_CLKLOS_TMR[4:0]
0x2C SW_REFINSEL[3:0] SW_LOS_CH_SEL[3:0]
0x2D RSRVD SW_ALLREFSON_TMR[4:0]
0x2E RSRVD OSCIN_PD_LDO OSCIN_SE_MODE OSCIN_BUF_TO_OSCOUT_EN OSCIN_OSCINSTAGE_EN OSCIN_BUF_REF_EN OSCIN_BUF_LOS_EN
0x2F OSCOUT_LVCMOS_WEAK_DRIVE OSCOUT_DIV_REGCONTROL OSCOUT_PINSEL_DIV[1:0] OSCOUT_SEL_VBG OSCOUT_DIV_CLKEN OSCOUT_SWRST OSCOUT_SEL_SRC
0x30 OSCOUT_DIV[7:0]
0x31 OSCOUT_DRV_MUTE[1:0] OSCOUT_DRV_MODE[5:0]
0x32 CH10_SWRST CH9_SWRST CH78_SWRST CH6_SWRST CH5_SWRST CH34_SWRST CH2_SWRST CH1_SWRST
0x33 OUTCH1_LDO_BYP_MODE OUTCH1_LDO_MASK RESERVED[5:0]
0x34 OUTCH1_DRIV_MODE[5:0] DIV_DCC_EN_CH1 OUTCH1_DIV_CLKEN
0x35 OUTCH2_LDO_BYP_MODE OUTCH2_LDO_MASK OUTCH2_DRIV_MODE[5:0]
0x36 RESERVED[5:0] DIV_DCC_EN_CH2 OUTCH2_DIV_CLKEN
0x37 OUTCH34_LDO_BYP_MODE OUTCH34_LDO_MASK OUTCH3_DRIV_MODE[5:0]
0x38 OUTCH4_DRIV_MODE[5:0] DIV_DCC_EN_CH3_4 OUTCH34_DIV_CLKEN
0x39 OUTCH5_LDO_BYP_MODE OUTCH5_LDO_MASK OUTCH5_DRIV_MODE[5:0]
0x3A DIV_DCC_EN_CH5 OUTCH5_DIV_CLKEN RESERVED[5:0]
0x3B OUTCH6_LDO_BYP_MODE OUTCH6_LDO_MASK RESERVED[5:0]
0x3C OUTCH6_DRIV_MODE[5:0] DIV_DCC_EN_CH6 OUTCH6_DIV_CLKEN
0x3D OUTCH78_LDO_BYP_MODE OUTCH78_LDO_MASK OUTCH7_DRIV_MODE[5:0]
0x3E OUTCH8_DRIV_MODE[5:0] DIV_DCC_EN_CH7_8 OUTCH78_DIV_CLKEN
0x3F OUTCH9_LDO_BYP_MODE OUTCH9_LDO_MASK RESERVED[5:0]
0x40 OUTCH9_DRIV_MODE[5:0] DIV_DCC_EN_CH9 OUTCH9_DIV_CLKEN
0x41 OUTCH10_LDO_BYP_MODE OUTCH10_LDO_MASK OUTCH10_DRIV_MODE[5:0]
0x42 RESERVED[5:0] DIV_DCC_EN_CH10 OUTCH10_DIV_CLKEN
0x43 OUTCH1_DIV[15:8]
0x44 OUTCH1_DIV[7:0]
0x45 OUTCH2_DIV[15:8]
0x46 OUTCH2_DIV[7:0]
0x47 OUTCH34_DIV[15:8]
0x48 OUTCH34_DIV[7:0]
0x49 OUTCH5_DIV[15:8]
0x4A OUTCH5_DIV[7:0]
0x4B OUTCH6_DIV[15:8]
0x4C OUTCH6_DIV[7:0]
0x4D OUTCH78_DIV[15:8]
0x4E OUTCH78_DIV[7:0]
0x4F OUTCH9_DIV[15:8]
0x50 OUTCH9_DIV[7:0]
0x51 OUTCH10_DIV[15:8]
0x52 OUTCH10_DIV[7:0]
0x53 OUTCH10_DIV_INV OUTCH9_DIV_INV OUTCH78_DIV_INV OUTCH6_DIV_INV OUTCH5_DIV_INV OUTCH34_DIV_INV OUTCH2_DIV_INV OUTCH1_DIV_INV
0x54 PLL1_F_30 PLL1_EN_REGULATION PLL1_PD_LD PLL1_DIR_POS_GAIN PLL1_LDO_WAIT_TMR[3:0]
0x55 PLL1_LCKDET_BY_32 PLL1_FAST_LOCK PLL1_LCKDET_LOS_MASK PLL1_FBCLK_INV RSRVD PLL1_BYP_LOS PLL1_PFD_UP_HOLDOVER PLL1_PFD_DOWN_HOLDOVER
0x56 RSRVD PLL1_LOL_NORESET PLL1_RDIV_CLKEN PLL1_RDIV_4CY PLL1_NDIV_CLKEN PLL1_NDIV_4CY
0x57 RSRVD PLL1_HOLDOVER_DLD_SWRST PLL1_RDIV_SWRST PLL1_NDIV_SWRST PLL1_HOLDOVERCNT_SWRST PLL1_HOLDOVER_LOCKDET_SWRST PLL1_SWRST
0x58 PLL1_LD_WNDW_SIZE[7:0]
0x59 PLL1_INTG_FL [3:0] PLL1_INTG [3:0]
0x5A RSRVD PLL1_PROP[6:0]
0x5B RSRVD PLL1_PROP_FL[6:0]
0x5C0x5C PLL1_HOLDOVER_EN PLL1_STARTUP_HOLDOVER_EN PLL1_HOLDOVER_FORCE PLL1_HOLDOVER_RAIL_MODE PLL1_HOLDOVER_MAX_CNT_EN PLL1_HOLDOVER_LOS_MASK PLL1_HOLDOVER_LCKDET_MASK PLL1_HOLDOVER_RAILDET_EN
0x5D PLL1_HOLDOVER_MAX_CNT[31:24]
0x5E PLL1_HOLDOVER_MAX_CNT[23:16]
0x5F PLL1_HOLDOVER_MAX_CNT[15:8]
0x60 PLL1_HOLDOVER_MAX_CNT[7:0]
0x61 PLL1_NDIV[15:8]
0x62 PLL1_NDIV[7:0]
0x63 PLL1_LOCKDET_CYC_CNT[23:16]
0x64 PLL1_LOCKDET_CYC_CNT[15:8]
0x65 PLL1_LOCKDET_CYC_CNT[7:0]
0x66 RSRVD
0x67 RSRVD
0x68 RSRVD
0x69 RSRVD
0x6A RSRVD PLL1_STORAGE_CELL[5:0]
0x6B RSRVD PLL1_RC_CLK_EN RSRVD PLL1_RC_CLK_DIV[2:0]
0x6C RSRVD PLL2_VCO_PRESC_LOW_POWER PLL2_BYP_OSC PLL2_BYP_TOP PLL2_BYP_BOT PLL2_GLOBAL_BYP
0x6D PLL2_EN_PULSE_GEN PLL2_RDIV_BYP PLL2_DBL_EN_INV PLL2_PD_VARBIAS PLL2_SMART_TRIM PLL2_LCKDET_LOS_MASK PLL2_RDIV_DBL_EN PLL2_PD_LD
0x6E PLL2_BYP_SYNC_TOP PLL2_BYP_SYNC_BOTTOM PLL2_EN_BYP_BUF PLL2_EN_BUF_SYNC_TOP PLL2_EN_BUF_SYNC_BOTTOM PLL2_EN_BUF_OSCOUT PLL2_EN_BUF_CLK_TOP PLL2_EN_BUF_CLK_BOTTOM
0x6F RSRVD PLL2_RDIV_SWRST PLL2_NDIV_SWRST PLL2_SWRST
0x70 PLL2_C4_LF_SEL[3:0] PLL2_R4_LF_SEL[3:0]
0x71 PLL2_C3_LF_SEL[3:0] PLL2_R3_LF_SEL[3:0]
0x72 RSRVD PLL2_PROP[5:0]
0x73 PLL2_NDIV[15:8]
0x74 PLL2_NDIV[7:0]
0x75 PLL2_RDIV[15:8]
0x76 PLL2_RDIV[7:0]
0x77 PLL2_STRG_INITVAL[15:8]
0x78 PLL2_STRG_INITVAL[7:0]
0x7D RSRVD RAILDET_UPP[5:0]
0x7E RSRVD RAILDET_LOW[5:0]
0x7F RSRVD PLL2_AC_CAL_EN PLL2_PD_AC PLL2_IDACSET_RECAL[1:0] PLL2_AC_REQ PLL2_FAST_ACAL
0x80 RSRVD PLL2_INTG[4:0]
0x81 RSRVD PLL2_AC_THRESHOLD[4:0]
0x82 RSRVD PLL2_AC_STRT_THRESHOLD[4:0]
0x83 PLL2_AC_CMP_WAIT[3:0] PLL2_AC_INIT_WAIT[3:0]
0x84 RSRVD PLL2_AC_JUMP_STEP[3:0]
0x85 PLL2_LD_WNDW_SIZE[7:0]
0x86 PLL2_LD_WNDW_SIZE_INITIAL[7:0]
0x87 PLL2_LOCKDET_CYC_CNT[23:16]
0x88 PLL2_LOCKDET_CYC_CNT[15:8]
0x89 PLL2_LOCKDET_CYC_CNT[7:0]
0x8A PLL2_LOCKDET_CYC_CNT_INITIAL[23:16]
0x8B PLL2_LOCKDET_CYC_CNT_INITIAL[15:8]
0x8C PLL2_LOCKDET_CYC_CNT_INITIAL[7:0]
0x8D SPI_EN_THREE_WIRE_IF RSRVD SPI_SDIO_OUTPUT_MUTE SPI_SDIO_OUTPUT_INV SPI_SDIO_OUTPUT_WEAK_DRIVE SPI_SDIO_EN_PULLUP SPI_SDIO_EN_PULLDOWN
0x8E RSRVD SPI_SCL_EN_PULLUP SPI_SCL_EN_PULLDOWN SPI_SCS_EN_PULLUP SPI_SCS_EN_PULLDOWN
0x8F RSRVD SPI_SDIO_OUTPUT_HIZ SPI_SDIO_ENB_INSTAGE SPI_SDIO_EN_ML_INSTAGE RSRVD SPI_SDIO_OUTPUT_DATA SPI_SDIO_INPUT_Y12 SPI_SDIO_INPUT_M12
0x90 RSRVD SPI_SCL_ENB_INSTAGE SPI_SCL_EN_ML_INSTAGE RSRVD SPI_SCL_INPUT_Y12 SPI_SCL_INPUT_M12
0x91 RSRVD SPI_SCS_ENB_INSTAGE SPI_SCS_EN_ML_INSTAGE RSRVD SPI_SCS_INPUT_Y12 SPI_SCS_INPUT_M12
0x92 STATUS0_MUX_SEL[2:0] STATUS0_OUTPUT_MUTE STATUS0_OUTPUT_INV STATUS0_OUTPUT_WEAK_DRIVE STATUS0_EN_PULLUP STATUS0_EN_PULLDOWN
0x93 STATUS1_MUX_SEL[2:0] STATUS1_OUTPUT_MUTE STATUS1_OUTPUT_INV STATUS1_OUTPUT_WEAK_DRIVE STATUS1_EN_PULLUP STATUS1_EN_PULLDOWN
0x94 STATUS1_INT_MUX[7:0]
0x95 STATUS0_INT_MUX[7:0]
0x96 RSRVD PLL2_REF_CLK_EN RSRVD PLL2_REF_STATCLK_DIV[2:0]
0x97 RSRVD STATUS0_OUTPUT_HIZ STATUS0_ENB_INSTAGE STATUS0_EN_ML_INSTAGE RSRVD STATUS0_OUTPUT_DATA STATUS0_INPUT_Y12 STATUS0_INPUT_M12
0x98 RSRVD STATUS1_OUTPUT_HIZ STATUS1_ENB_INSTAGE STATUS1_EN_ML_INSTAGE RSRVD STATUS1_OUTPUT_DATA STATUS1_INPUT_Y12 STATUS1_INPUT_M12
0x99 SYNC_MUX_SEL[2:0] SYNC_OUTPUT_MUTE SYNC_OUTPUT_INV SYNC_OUTPUT_WEAK_DRIVE SYNC_EN_PULLUP SYNC_EN_PULLDOWN
0x9A RSRVD RSRVD
0x9B RSRVD CLKINSEL1_EN_PULLUP CLKINSEL1_EN_PULLDOWN
0x9C RSRVD CLKINSEL1_ENB_INSTAGE CLKINSEL1_EN_ML_INSTAGE RSRVD CLKINSEL1_INPUT_Y12 CLKINSEL1_INPUT_M12
0xAC PLL1_TSTMODE_REF_FB_EN RSRVD
0xAD RSRVD RESET_PLL2_DLD[1:0] RSRVD PLL2_TSTMODE_REF_FB_EN PD_VCO_LDO[1:0]
0xBE RSRVD LOS HOLDOVER_DLD HOLDOVER_LOL HOLDOVER_LOS PLL2_LCK_DET PLL1_LCK_DET
0xF6 RSRVD PLL2_DLD_EN RSRVD
0xFD OUTCH1_DDLY[7:0]
0xFF OUTCH2_DDLY[7:0]
0x101 OUTCH34_DDLY[7:0]
0x103 OUTCH5_DDLY[7:0]
0x105 OUTCH6_DDLY[7:0]
0x107 OUTCH78_DDLY[7:0]
0x109 OUTCH9_DDLY[7:0]
0x10B OUTCH10_DDLY[7:0]
0x10D RSRVD CH1_ADLY[4:0] CH1_ADLY_EN RSRVD
0x10E RSRVD CH2_ADLY[4:0] CH2_ADLY_EN RSRVD
0x110 RSRVD CH3_ADLY[4:0] CH3_ADLY_EN RSRVD
0x111 RSRVD CH4_ADLY[4:0] CH4_ADLY_EN RSRVD
0x112 RSRVD CH5_ADLY[4:0] CH5_ADLY_EN RSRVD
0x115 RSRVD CH6_ADLY[4:0] CH6_ADLY_EN RSRVD
0x116 RSRVD CH7_ADLY[4:0] CH7_ADLY_EN RSRVD
0x117 RSRVD CH8_ADLY[4:0] CH8_ADLY_EN RSRVD
0x119 RSRVD CH9_ADLY[4:0] CH9_ADLY_EN RSRVD
0x11A RSRVD CH10_ADLY[4:0] CH10_ADLY_EN RSRVD
0x124 RSRVD CLKMUX[3:0]
0x127 SYSREF_BYP_DYNDIGDLY_GATING_CH1 SYSREF_BYP_ANALOGDLY_GATING_CH1 SYNC_EN_CH1 HS_EN_CH1 DRIV_1_SLEW[1:0] RSRVD
0x128 SYSREF_BYP_DYNDIGDLY_GATING_CH2 SYSREF_BYP_ANALOGDLY_GATING_CH2 SYNC_EN_CH2 HS_EN_CH2 RSRVD DRIV_2_SLEW[1:0]
0x129 SYSREF_BYP_DYNDIGDLY_GATING_CH3_4 SYSREF_BYP_ANALOGDLY_GATING_CH3_4 SYNC_EN_CH3_4 HS_EN_CH3_4 DRIV_4_SLEW[1:0] DRIV_3_SLEW[1:0]
0x12A SYSREF_BYP_DYNDIGDLY_GATING_CH5 SYSREF_BYP_ANALOGDLY_GATING_CH5 SYNC_EN_CH5 HS_EN_CH5 RSRVD DRIV_5_SLEW[1:0]
0x12B SYSREF_BYP_DYNDIGDLY_GATING_CH6 SYSREF_BYP_ANALOGDLY_GATING_CH6 SYNC_EN_CH6 HS_EN_CH6 DRIV_6_SLEW[1:0] RSRVD
0x12C SYSREF_BYP_DYNDIGDLY_GATING_CH7_8 SYSREF_BYP_ANALOGDLY_GATING_CH7_8 SYNC_EN_CH7_8 HS_EN_CH7_8 DRIV_8_SLEW[1:0] DRIV_7_SLEW[1:0]
0x12D SYSREF_BYP_DYNDIGDLY_GATING_CH9 SYSREF_BYP_ANALOGDLY_GATING_CH9 SYNC_EN_CH9 HS_EN_CH9 DRIV_9_SLEW[1:0] RSRVD
0x12E SYSREF_BYP_DYNDIGDLY_GATING_CH10 SYSREF_BYP_ANALOGDLY_GATING_CH10 SYNC_EN_CH10 HS_EN_CH10 RSRVD DRIV_10_SLEW[1:0]
0x130 RSRVD DYN_DDLY_CH1[2:0]
0x131 RSRVD DYN_DDLY_CH2[2:0]
0x133 RSRVD DYN_DDLY_CH3[2:0]
0x134 RSRVD DYN_DDLY_CH4[2:0]
0x135 RSRVD DYN_DDLY_CH5[2:0]
0x138 RSRVD DYN_DDLY_CH6[2:0]
0x139 RSRVD DYN_DDLY_CH7[2:0]
0x13A RSRVD DYN_DDLY_CH8[2:0]
0x13C RSRVD DYN_DDLY_CH9[2:0]
0x13D RSRVD DYN_DDLY_CH10[2:0]
0x140 RSRVD OUTCH_SYSREF_PLSCNT[5:0]
0x141 SYNC_INT_MUX[7:0]
0x142 RSRVD SYNC_OUTPUT_HIZ SYNC_ENB_INSTAGE SYNC_EN_ML_INSTAGE RSRVD SYNC_OUTPUT_DATA SYNC_INPUT_Y12 SYNC_INPUT_M12
0x143 RSRVD FBBUF_CH5_EN RSRVD FBBUF_CH6_EN
0x146 RSRVD PLL2_NBYPASS_DIV2_FB PLL2_PRESCALER[3:0] PLL2_FBDIV_MUXSEL[1:0]
0x149 RSRVD PLL1_CLKINSEL1_ML_HOLDOVER PLL1_SYNC_HOLDOVER PLL1_STATUS1_HOLDOVER PLL1_STATUS0_HOLDOVER
0x14A RSRVD SYNC_ANALOGDLY[4:0] SYNC_ANALOGDLY_EN SYNC_INV
0x14B RESERVED DYN_DDLY_CH10_EN DYN_DDLY_CH9_EN RESERVED DYN_DDLY_CH8_EN DYN_DDLY_CH7_EN DYN_DDLY_CH6_EN RESERVED
0x14C DYN_DDLY_CH5_EN DYN_DDLY_CH4_EN DYN_DDLY_CH3_EN RESERVED DYN_DDLY_CH2_EN DYN_DDLY_CH1_EN RESERVED RESERVED
0x14E SYSREF_EN_CH10 SYSREF_EN_CH9 SYSREF_EN_CH7_8 SYSREF_EN_CH6 SYSREF_EN_CH5 SYSREF_EN_CH3_4 SYSREF_EN_CH2 SYSREF_EN_CH1
0x150 RSRVD PLL2_PFD_DIS_SAMPLE PLL2_PROG_PFD_RESET[2:0]
0x151 RSRVD PLL2_RFILT RSRVD PLL2_CP_EN_SAMPLE_BYP PLL2_CPROP[1:0]
0x152 RSRVD PLL2_EN_FILTER PLL2_CSAMPLE[2:0]
0x153 RSRVD PLL2_CFILT