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LMK04610

ACTIVE

Ultra low-noise and low power JESD204B compliant clock jitter cleaner with dual PLLs

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Data sheet

LMK04610

ACTIVE
Data sheet Order now

Product details

Number of input channels 2 Number of outputs 10 RMS jitter (fs) 65 Features JESD204B Output frequency (min) (MHz) 0.03 Output frequency (max) (MHz) 2000 Output type LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85
Number of input channels 2 Number of outputs 10 RMS jitter (fs) 65 Features JESD204B Output frequency (min) (MHz) 0.03 Output frequency (max) (MHz) 2000 Output type LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85
VQFN (RTQ) 56 64 mm² (8 mm × 8 mm)
  • Dual-loop PLL architecture
  • Ultra low noise (10 kHz to 20 MHz):
    • 48-fs RMS jitter at 1966.08 MHz
    • 50-fs RMS jitter at 983.04 MHz
    • 61-fs RMS jitter at 122.88 MHz
  • –165-dBc/Hz noise floor at 122.88 MHz
  • JESD204B support
    • Single shot, pulsed, and continuous SYSREF
  • 10 differential output clocks in 8 frequency groups
    • Programmable output swing between 700 mVpp to 1600 mVpp
    • Each output pair can be configured to SYSREF clock output
    • 16-bit channel divider
    • Minimum SYSREF frequency of 25 kHz
    • Maximum output frequency of 2 GHz
    • Precision digital delay, dynamically adjustable
      • Digital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)
    • 60-ps step analog delay
    • 50% duty cycle output divides, 1 to 65535
      (even and odd)
  • Two reference inputs
    • Holdover mode, when inputs are lost
    • Automatic and manual switch-over modes
    • Loss-of-signal (LOS) detection
  • 0.88-W typical power consumption with 10 outputs active
  • Operates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)
  • Fully integrated programmable loop filter
  • PLL2
    • PLL2 phase detector rate up to 250 MHz
    • OSCin frequency-doubler
    • Integrated low-noise VCO
  • Internal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs
  • 3- or 4-wire SPI interface (4-wire is default)
  • –40ºC to +85ºC industrial ambient temperature
  • Supports 105ºC PCB temperature (measured at thermal pad)
  • LMK04610: 8-mm × 8-mm VQFN-56 package with 0.5-mm pitch
  • Dual-loop PLL architecture
  • Ultra low noise (10 kHz to 20 MHz):
    • 48-fs RMS jitter at 1966.08 MHz
    • 50-fs RMS jitter at 983.04 MHz
    • 61-fs RMS jitter at 122.88 MHz
  • –165-dBc/Hz noise floor at 122.88 MHz
  • JESD204B support
    • Single shot, pulsed, and continuous SYSREF
  • 10 differential output clocks in 8 frequency groups
    • Programmable output swing between 700 mVpp to 1600 mVpp
    • Each output pair can be configured to SYSREF clock output
    • 16-bit channel divider
    • Minimum SYSREF frequency of 25 kHz
    • Maximum output frequency of 2 GHz
    • Precision digital delay, dynamically adjustable
      • Digital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)
    • 60-ps step analog delay
    • 50% duty cycle output divides, 1 to 65535
      (even and odd)
  • Two reference inputs
    • Holdover mode, when inputs are lost
    • Automatic and manual switch-over modes
    • Loss-of-signal (LOS) detection
  • 0.88-W typical power consumption with 10 outputs active
  • Operates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)
  • Fully integrated programmable loop filter
  • PLL2
    • PLL2 phase detector rate up to 250 MHz
    • OSCin frequency-doubler
    • Integrated low-noise VCO
  • Internal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs
  • 3- or 4-wire SPI interface (4-wire is default)
  • –40ºC to +85ºC industrial ambient temperature
  • Supports 105ºC PCB temperature (measured at thermal pad)
  • LMK04610: 8-mm × 8-mm VQFN-56 package with 0.5-mm pitch

The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support.

The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support.

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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs datasheet (Rev. B) PDF | HTML Jan 9, 2018
Application note JESD204B Multi-Device Synchronization Using LMK0461x PDF | HTML Aug 16, 2017
Application note LMK0461x Phase Noise Performance With DC-DC Converters (Rev. B) Jul 20, 2017
Application note SDPLL for LMK046xx Family May 15, 2017

Design & development

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Evaluation board

LMK04610EVM — LMK04610 Ultra Low-Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual PLLs EVM

The LMK04610EVM features LMK04610 ultra Low-noise and low power JESD204B compliant Dual Loop Jitter Cleaner. With a power consumption of only 900 mW with all outputs running, LMK04610 supports sub-74 fs jitter (12 kHz to 20 MHz) using a low noise VCXO module. Integrated LDOs provide high PSRR that (...)
User guide: PDF
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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

Supported products & hardware
Simulation model

LMK0461X IBIS Model

SNAM204.ZIP (126 KB) - IBIS model
Supported products & hardware
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.

Supported products & hardware
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VQFN (RTQ) 56 Ultra Librarian
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