Ultra low-noise and low power JESD204B compliant clock jitter cleaner with dual PLLs


Product details


Function Dual-loop PLL Number of outputs 10 RMS jitter (fs) 65 Output frequency (Min) (MHz) 0.03 Output frequency (Max) (MHz) 2000 Input type LVCMOS, LVDS, LVPECL Output type LVDS, LVPECL Supply voltage (Min) (V) 1.7 Supply voltage (Max) (V) 3.465 Features JESD204B Operating temperature range (C) -40 to 85 open-in-new Find other Clock jitter cleaners & synchronizers

Package | Pins | Size

VQFN (RTQ) 56 64 mm² 8 x 8 open-in-new Find other Clock jitter cleaners & synchronizers


  • Dual-loop PLL architecture
  • Ultra low noise (10 kHz to 20 MHz):
    • 48-fs RMS jitter at 1966.08 MHz
    • 50-fs RMS jitter at 983.04 MHz
    • 61-fs RMS jitter at 122.88 MHz
  • –165-dBc/Hz noise floor at 122.88 MHz
  • JESD204B support
    • Single shot, pulsed, and continuous SYSREF
  • 10 differential output clocks in 8 frequency groups
    • Programmable output swing between 700 mVpp to 1600 mVpp
    • Each output pair can be configured to SYSREF clock output
    • 16-bit channel divider
    • Minimum SYSREF frequency of 25 kHz
    • Maximum output frequency of 2 GHz
    • Precision digital delay, dynamically adjustable
      • Digital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)
    • 60-ps step analog delay
    • 50% duty cycle output divides, 1 to 65535
      (even and odd)
  • Two reference inputs
    • Holdover mode, when inputs are lost
    • Automatic and manual switch-over modes
    • Loss-of-signal (LOS) detection
  • 0.88-W typical power consumption with 10 outputs active
  • Operates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)
  • Fully integrated programmable loop filter
  • PLL2
    • PLL2 phase detector rate up to 250 MHz
    • OSCin frequency-doubler
    • Integrated low-noise VCO
  • Internal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs
  • 3- or 4-wire SPI interface (4-wire is default)
  • –40ºC to +85ºC industrial ambient temperature
  • Supports 105ºC PCB temperature (measured at thermal pad)
  • LMK04610: 8-mm × 8-mm VQFN-56 package with 0.5-mm pitch

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The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support.

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Technical documentation

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Type Title Date
* Data sheet LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs datasheet (Rev. B) Jan. 09, 2018
Application note LMK0461x Phase Noise Performance With DC-DC Converters (Rev. B) Jul. 20, 2017
Application note SDPLL for LMK046xx Family May 15, 2017
User guide LMK04610 Evaluation Board User's Guide (Rev. A) Feb. 01, 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
The LMK04610EVM features LMK04610 ultra Low-noise and low power JESD204B compliant Dual Loop Jitter Cleaner. With a power consumption of only 900 mW with all outputs running, LMK04610 supports sub-74 fs jitter (12 kHz to 20 MHz) using a low noise VCXO module. Integrated LDOs provide high PSRR that (...)
  • Dual Loop Architecture with typical 60 fs rms from 10 kHz to 20 MHz  at 122.88 MHz output frequency
  • Integrated Loopfilter support easy prototyping
  • 0.9 W typical power consumption for 10 outputs at 122.88 MHz
  • Jumper configurable supplies with on-board LDOs and DCDC converters
  • GUI platform for full access (...)

Software development

Texas Instruments Clocks and Synthesizers (TICS) Pro Software
TICSPRO-SW The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
  • Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
  • Export programming configurations for use in end application.

Design tools & simulation

SNAM204.ZIP (126 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
  • Presents clear and intuitive block (...)

CAD/CAE symbols

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QFN (RTQ) 56 View options

Ordering & quality

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