SNAS801B June   2020  – June 2021 LMK05318B

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1. 6.1 Device Start-Up Modes
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: 4-Layer JEDEC Standard PCB
    5. 7.5 Thermal Information: 10-Layer Custom PCB
    6. 7.6 Electrical Characteristics
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Output Clock Test Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 ITU-T G.8262 (SyncE) Standards Compliance
    2. 9.2 Functional Block Diagram
      1. 9.2.1 PLL Architecture Overview
      2. 9.2.2 DPLL Mode
      3. 9.2.3 APLL-Only Mode
    3. 9.3 Feature Description
      1. 9.3.1  Oscillator Input (XO_P/N)
      2. 9.3.2  Reference Inputs (PRIREF_P/N and SECREF_P/N)
        1. 9.3.2.1 Programmable Input Hysteresis
      3. 9.3.3  Clock Input Interfacing and Termination
      4. 9.3.4  Reference Input Mux Selection
        1. 9.3.4.1 Automatic Input Selection
        2. 9.3.4.2 Manual Input Selection
      5. 9.3.5  Hitless Switching
        1. 9.3.5.1 Hitless Switching With 1-PPS Inputs
      6. 9.3.6  Gapped Clock Support on Reference Inputs
      7. 9.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 9.3.7.1 XO Input Monitoring
        2. 9.3.7.2 Reference Input Monitoring
          1. 9.3.7.2.1 Reference Validation Timer
          2. 9.3.7.2.2 Amplitude Monitor
          3. 9.3.7.2.3 Frequency Monitoring
          4. 9.3.7.2.4 Missing Pulse Monitor (Late Detect)
          5. 9.3.7.2.5 Runt Pulse Monitor (Early Detect)
          6. 9.3.7.2.6 Phase Valid Monitor for 1-PPS Inputs
        3. 9.3.7.3 PLL Lock Detectors
        4. 9.3.7.4 Tuning Word History
        5. 9.3.7.5 Status Outputs
        6. 9.3.7.6 Interrupt
      8. 9.3.8  PLL Relationships
        1. 9.3.8.1  PLL Frequency Relationships
        2. 9.3.8.2  Analog PLLs (APLL1, APLL2)
        3. 9.3.8.3  APLL Reference Paths
          1. 9.3.8.3.1 APLL XO Doubler
          2. 9.3.8.3.2 APLL1 XO Reference (R) Divider
          3. 9.3.8.3.3 APLL2 Reference (R) Dividers
        4. 9.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 9.3.8.5  APLL Feedback Divider Paths
          1. 9.3.8.5.1 APLL1 N Divider With SDM
          2. 9.3.8.5.2 APLL2 N Divider With SDM
        6. 9.3.8.6  APLL Loop Filters (LF1, LF2)
        7. 9.3.8.7  APLL Voltage Controlled Oscillators (VCO1, VCO2)
          1. 9.3.8.7.1 VCO Calibration
        8. 9.3.8.8  APLL VCO Clock Distribution Paths (P1, P2)
        9. 9.3.8.9  DPLL Reference (R) Divider Paths
        10. 9.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 9.3.8.11 DPLL Loop Filter (DLF)
        12. 9.3.8.12 DPLL Feedback (FB) Divider Path
      9. 9.3.9  Output Clock Distribution
      10. 9.3.10 Output Channel Muxes
      11. 9.3.11 Output Dividers (OD)
      12. 9.3.12 Clock Outputs (OUTx_P/N)
        1. 9.3.12.1 AC-Differential Output (AC-DIFF)
        2. 9.3.12.2 HCSL Output
        3. 9.3.12.3 1.8-V LVCMOS Output
        4. 9.3.12.4 Output Auto-Mute During LOL
      13. 9.3.13 Glitchless Output Clock Start-Up
      14. 9.3.14 Clock Output Interfacing and Termination
      15. 9.3.15 Output Synchronization (SYNC)
      16. 9.3.16 Zero-Delay Mode (ZDM) Synchronization for 1-PPS Input and Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Start-Up Modes
        1. 9.4.1.1 EEPROM Mode
        2. 9.4.1.2 ROM Mode
      2. 9.4.2 PLL Operating Modes
        1. 9.4.2.1 Free-Run Mode
        2. 9.4.2.2 Lock Acquisition
        3. 9.4.2.3 Locked Mode
        4. 9.4.2.4 Holdover Mode
      3. 9.4.3 PLL Start-Up Sequence
      4. 9.4.4 Digitally-Controlled Oscillator (DCO) Mode
        1. 9.4.4.1 DCO Frequency Step Size
        2. 9.4.4.2 DCO Direct-Write Mode
      5. 9.4.5 Zero-Delay Mode Synchronization
    5. 9.5 Programming
      1. 9.5.1 Interface and Control
      2. 9.5.2 I2C Serial Interface
        1. 9.5.2.1 I2C Block Register Transfers
      3. 9.5.3 SPI Serial Interface
        1. 9.5.3.1 SPI Block Register Transfer
      4. 9.5.4 Register Map and EEPROM Map Generation
      5. 9.5.5 General Register Programming Sequence
      6. 9.5.6 EEPROM Programming Flow
        1. 9.5.6.1 EEPROM Programming Using Method #1 (Register Commit)
          1. 9.5.6.1.1 Write SRAM Using Register Commit
          2. 9.5.6.1.2 Program EEPROM
        2. 9.5.6.2 EEPROM Programming Using Method #2 (Direct Writes)
          1. 9.5.6.2.1 Write SRAM Using Direct Writes
          2. 9.5.6.2.2 User-Programmable Fields In EEPROM
      7. 9.5.7 Read SRAM
      8. 9.5.8 Read EEPROM
      9. 9.5.9 EEPROM Start-Up Mode Default Configuration
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Device Start-Up Sequence
      2. 10.1.2 Power Down (PDN) Pin
      3. 10.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 10.1.3.1 Mixing Supplies
        2. 10.1.3.2 Power-On Reset (POR) Circuit
        3. 10.1.3.3 Powering Up From a Single-Supply Rail
        4. 10.1.3.4 Power Up From Split-Supply Rails
        5. 10.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
      4. 10.1.4 Slow or Delayed XO Start-Up
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Bypassing
    2. 11.2 Device Current and Power Consumption
      1. 11.2.1 Current Consumption Calculations
      2. 11.2.2 Power Consumption Calculations
      3. 11.2.3 Example
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Reliability
      1. 12.3.1 Support for PCB Temperature up to 105 °C
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 TICS Pro
      2. 13.1.2 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Electrical Characteristics

Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY CHARACTERISTICS
IDD_DIG Core Current Consumption
(VDD_DIG)		 21 mA
IDD_IN Core Current Consumption
(VDD_IN)		 43 mA
IDD_PLL1 Core Current Consumption
(VDD_PLL1)		 DPLL and APLL1 enabled 110 mA
IDD_XO Core Current Consumption
(VDD_XO)		 20 mA
IDD_PLL2 Core Current Consumption
(VDD_PLL2)		 APLL2 disabled 20 mA
APLL2 enabled 120 mA
IDDO_x Output Current Consumption, per channel(3)
(VDDO_x)		 Output mux and divider enabled, excludes driver(s)
Divider value = 2 to 6		 65 mA
Output mux and divider enabled, excludes driver(s)
Divider value > 6		 70 mA
AC-LVDS 11 mA
AC-CML 16 mA
AC-LVPECL 18 mA
HCSL, 50-Ω load to GND 25 mA
1.8-V LVCMOS (x2), 100 MHz 6 mA
IDDPDN Total Current Consumption (all VDD and VDDO pins, 3.3 V) Device powered-down (PDN pin held low) 56 mA
XO INPUT CHARACTERISTICS (XO)
fIN Input frequency range   10   100 MHz
VIN-SE Single-ended input voltage swing LVCMOS input, DC-coupled to XO_P 1   2.6 Vpp
VIN-DIFF Differential input voltage swing(11) Differential input 0.4   2 Vpp
VID Differential input voltage swing(11) Differential input 0.2 1 |V|
dV/dt Input slew rate(13)   0.2 0.5   V/ns
IDC Input duty cycle   40   60 %
IIN Input leakage 50-Ω and 100-Ω internal terminations disabled –350   350 µA
REFERENCE INPUT CHARACTERISTICS (PRIREF, SECREF)
fIN Input frequency range Differential input(4) 5   800 MHz
Input frequency range LVCMOS input 1E–6   250 MHz
VIH Input high voltage LVCMOS input, DC-coupled to REF_P. Internally DC-coupled 1.8     V
VIL Input low voltage LVCMOS input, DC-coupled to REF_P. Internally DC-coupled   0.6 V
VIN-SE Single-ended input voltage swing LVCMOS input, DC-coupled to REF_P. Internally AC-coupled 1   2.6 Vpp
VIN-DIFF Differential input voltage swing(11) Differential input, , VHYST = 50 mV 0.4   2 Vpp
Differential input voltage swing(11) Differential input, , VHYST = 200 mV 0.7   2 Vpp
VID Differential input voltage swing(11) Differential input, VHYST = 50 mV 0.2 1 V
Differential input voltage swing(11) Differential input, VHYST = 200 mV 0.35 1 V
dV/dt Input slew rate(13)   0.2 0.5   V/ns
IIN Input leakage 50-Ω and 100-Ω internal terminations disabled –350   350 µA
VCO CHARACTERISTICS
fVCO1 VCO1 Frequency Range 2499.750 2500 2500.250 MHz
fVCO2 VCO2 Frequency Range 5500 6250 MHz
APLL CHARACTERISTICS
fPD1 APLL1 Phase Detector Frequency 1 80 MHz
fPD2 APLL2 Phase Detector Frequency 10 150 MHz
AC-LVDS OUTPUT CHARACTERISTICS (OUTx)
fOUT Output frequency(5)       1250 MHz
VOD Output voltage swing (VOH - VOL) 25 MHz ≤ fOUT ≤ 800 MHz; TYP at 156.25 MHz 250 390 450 mV
 fOUT = 50 MHz 285 400 450
100 MHz ≤ fOUT ≤ 200 MHz 275 390 450
fOUT = 312.5 270 385 450
fOUT = 1250 MHz 280
VOUT-DIFF Differential output voltage swing, peak-to-peak   2×VOD   Vpp
VOS Output common mode   100   430 mV
tSK Output-to-output skew Same post divider, output divide values, and output type     100 ps
tR/tF Output rise/fall time(12) 20% to 80%, < 300 MHz   225 350 ps
± 100 mV around center point, 300 MHz ≤ fOUT ≤ 800 MHz   85 250 ps
PNFLOOR Output phase noise floor fOUT = 156.25 MHz;  fOFFSET > 10 MHz   -160   dBc/Hz
ODC Output duty cycle(9)   45   55 %
AC-CML OUTPUT CHARACTERISTICS (OUTx)
fOUT Output frequency(5)       1250 MHz
VOD Output voltage swing (VOH - VOL) 25 MHz ≤ fOUT ≤ 800 MHz; TYP at fOUT = 156.25 MHz 400 600 800 mV
fOUT = 50 MHz 500 620 700
100 MHz ≤ fOUT ≤ 200 MHz 490 600 690
fOUT = 312.5 480 580 680
fOUT = 1250 MHz 400
VOUT-DIFF Differential output voltage swing, peak-to-peak   2×VOD   Vpp
VOS Output common mode   150   550 mV
tSK Output-to-output skew Same post divider, output divide values, and output type     100 ps
tR/tF Output rise/fall time(12) 20% to 80%, < 300 MHz   225 300 ps
± 100 mV around center point, 300 MHz ≤ fOUT ≤ 800 MHz   50 150 ps
PNFLOOR Output phase noise floor fOUT = 156.25 MHz; fOFFSET > 10 MHz   -160 dBc/Hz
ODC Output duty cycle(9)   45   55 %
AC-LVPECL OUTPUT CHARACTERISTICS (OUTx)
fOUT Output frequency(5)       1250 MHz
VOD Output voltage swing (VOH - VOL) 25 MHz ≤ fOUT ≤ 800 MHz; TYP at fOUT = 156.25 MHz 500 780 1000 mV
fOUT = 50 MHz 660 810 920
100 MHz ≤ fOUT ≤ 200 MHz 640 780 900
fOUT = 312.5 MHz 620 740 880
fOUT = 1250 MHz 510
VOUT-DIFF Differential output voltage swing, peak-to-peak   2×VOD   Vpp
VOS Output common mode   300   700 mV
tSK Output-to-output skew Same post divider, output divide values, and output type     100 ps
tR/tF Output rise/fall time(12) 20% to 80%, < 300 MHz   200 300 ps
± 100 mV around center point, 300 MHz ≤ fOUT ≤ 800 MHz   35 100 ps
PNFLOOR Output phase noise floor fOUT = 156.25 MHz; fOFFSET > 10 MHz   –162   dBc/Hz
ODC Output duty cycle(9) 45   55 %
HCSL OUTPUT CHARACTERISTICS (OUTx)
fOUT Output frequency(5)       400 MHz
VOH Output high voltage   600   880 mV
VOL Output low voltage   –150   150 mV
tSK Output-to-output skew Same post divider, output divide values, and output type     100 ps
dV/dt Output slew rate(12) ± 150 mV around center point 1.6   4 V/ns
PNFLOOR Output phase noise floor (fOFFSET > 10 MHz) 100 MHz   –160   dBc/Hz
ODC Output duty cycle(9) 45 55 %
1.8-V LVCMOS OUTPUT CHARACTERISTICS (OUT[4:7])
fOUT Output frequency   1E–6   200 MHz
VOH Output high voltage IOH = 1 mA 1.2     V
VOL Output low voltage IOL = 1 mA     0.4 V
IOH Output high current     –23   mA
IOL Output low current   20   mA
tR/tF Output rise/fall time 20% to 80%   250   ps
tSK Output-to-output skew Same post divider, output divide values, and output type     100 ps
Output-to-output skew Same post divider, output divide values, LVCMOS-to-DIFF     1.5 ns
PNFLOOR Output phase noise floor fOUT = 66.66 MHz; fOFFSET > 10 MHz -160   dBc/Hz
ODC Output duty cycle(9)   45 55 %
ROUT Output impedance   50   Ω
3-LEVEL LOGIC INPUT CHARACTERISTICS (HW_SW_CTRL, GPIO1, REFSEL, STATUS[1:0])
VIH Input high voltage   1.4     V
VIM Input mid voltage Input floating with internal bias and PDN pulled low 0.7   0.9 V
VIL Input low voltage       0.4 V
IIH Input high current VIH = VDD –40   40 µA
IIL Input low current VIL = GND –40   40 µA
2-LEVEL LOGIC INPUT CHARACTERISTICS (PDN, GPIO[2:0], SDI, SCK, SCS)
VIH Input high voltage   1.2     V
VIL Input low voltage       0.6 V
IIH Input high current VIH = VDD -40   40 µA
IIL Input low current VIL = GND -40   40 µA
LOGIC OUTPUT CHARACTERISTICS (STATUS[1:0], SDO)
VOH Output high voltage IOH = 1 mA 1.2 V
VOL Output low voltage IOL = 1 mA 0.6 V
tR/tF Output rise/fall time 20% to 80%, LVCMOS mode, 1 kΩ to GND   500   ps
SPI TIMING REQUIREMENTS (SDI, SCK, SCS, SDO)
fSCK SPI clock rate     20 MHz
SPI clock rate; NVM write 5 MHz
t1 SCS to SCK setup time   10   ns
t2 SDI to SCK setup time   10     ns
t3 SDI to SCK hold time   10     ns
t4 SCK high time   25     ns
t5 SCK low time   25     ns
t6 SCK to SDO valid read-back data     20 ns
t7 SCS pulse width   20     ns
t8 SDI to SCK hold time   10     ns
I2C-COMPATIBLE INTERFACE CHARACTERISTICS (SDA, SCL)
VIH Input high voltage   1.2     V
VIL Input low voltage        0.6 V
IIH Input leakage   –15   15 µA
VOL Output low voltage IOL = 3 mA     0.3 V
fSCL I2C clock rate Standard     100 kHz
Fast mode     400
tSU(START) START condition setup time SCL high before SDA low 0.6     µs
tH(START) START condition hold time SCL low after SDA low 0.6     µs
tW(SCLH) SCL pulse width high   0.6     µs
tW(SCLL) SCL pulse width low   1.3     µs
tSU(SDA) SDA setup time   100     ns
tH(SDA) SDA hold time SDA valid after SCL low 0   0.9 µs
tR(IN) SDA/SCL input rise time       300 ns
tF(IN) SDA/SCL input fall time       300 ns
tF(OUT) SDA output fall time CBUS ≤ 400 pF     300 ns
tSU(STOP) STOP condition setup time   0.6     µs
tBUS Bus free time between STOP and START   1.3     µs
POWER SUPPLY NOISE REJECTION (PSNR) / CROSSTALK SPURS
PSNR50mV Spur induced by power supply noise (VN = 50 mVpp) (6) (7) VDD = 3.3 V, VDDO_x = 3.3 V, 156.25 MHz, AC-DIFF output –83 dBc
VDD = 3.3 V, VDDO_x = 3.3 V, 156.25 MHz, HCSL output –78 dBc
PSNR25mV Spur induced by power supply noise (VN = 25 mVpp)(6) (7) VDD = 3.3 V, VDDO_x = 1.8 V, 156.25 MHz, AC-DIFF output –63 dBc
VDD = 3.3 V, VDDO_x = 1.8 V, 156.25 MHz, HCSL output –58 dBc
VDD = 3.3 V, VDDO_x = 1.8 V, 156.25 MHz, LVCMOS output –45 dBc
SPURXTALK Spur level due to output-to-output crosstalk (adjacent channels)(7) fOUTx = 156.25 MHz, fOUTy = 155.52 MHz, AC-LVPECL –75 dBc
SPUR Highest spur level within 12 kHz to 40 MHz band (excludes output crosstalk and integer-boundary spurs)(7) fVCO1 = 2500 MHz, fVCO2 = 6065.28 MHz, fOUTx = 156.25 MHz, fOUTy = 155.52 MHz, AC-LVPECL  –80 dBc
PLL CLOCK OUTPUT PERFORMANCE CHARACTERISTICS
RJ RMS Phase Jitter (12 kHz to 20 MHz)(14) 312.5 MHz AC-LVPECL output from APLL1, fXO = 48.0048 MHz, fPD1 = fXO/2, fVCO1 = 2.5 GHz 50 80 fs RMS
RMS Phase Jitter (12 kHz to 20 MHz)(14) 156.25 MHz AC-LVPECL output from APLL1, fXO = 48.0048 MHz, fPD1 = fXO/2, fVCO1 = 2.5 GHz 60 90 fs RMS
RMS Phase Jitter (12 kHz to 20 MHz)(14) 153.6 MHz AC-LVPECL output from APLL2, fXO = 48.0048 MHz, fPD1 = fXO/2, fVCO1 = 2.5 GHz, fPD2 = fVCO1/18, fVCO2 = 5.5296 GHz 125 200 fs RMS
RMS Phase Jitter (12 kHz to 20 MHz)(14) 155.52 MHz AC-LVPECL output from APLL2, fXO = 48.0048 MHz, fPD1 = fXO/2, fVCO1 = 2.5 GHz, fPD2 = fVCO1/18, fVCO2 = 5.59872 GHz 125 200 fs RMS
BW DPLL bandwidth range(8) Programmed bandwidth setting 0.01 4000 Hz
JPK DPLL closed-loop jitter peaking(10) fREF = 25 MHz, fOUT = 10 MHz, DPLL BW = 0.1 Hz or 10 Hz   0.1   dB
JTOL Jitter tolerance Jitter modulation = 10 Hz, 25.78125 Gbps 6455   UI p-p
tHITLESS Phase hit between two reference inputs with 0 ppm error Valid for a single switchover event between two clock inputs at the same frequency ± 50 ps
fHITLESS Frequency transient during hitless switch Valid for a single switchover event between two clock inputs at the same frequency ± 10 ppb
(1) Total device current can be estimated by summing the individual IDD_x and IDDO_x per pin for all blocks enabled in a given configuration.
(5) Configuration A (All PLL blocks on except APLL2 is disabled): fREF = 25 MHz, fXO = 48.0048 MHz, fVCO1 = 2.5 GHz.
(5) Configuration B (All PLL blocks on): fREF = 25 MHz, fXO = 48.0048 MHz, fVCO1 = 2.5 GHz, fVCO2 = 5598.72 GHz, PLL2_P1 = 3.
(6) IDDO_x current for an operating output is the sum of mux, divider, and an output format.
(8) For a differential input clock below 5 MHz, TI recommends to disable the differential input amplitude monitor and enable at least one other monitor (frequency, window detectors) to validate the input clock.  Otherwise, consider using an LVCMOS clock for an input below 5 MHz.
(5) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min specification.
(6) PSNR is the single-sideband spur level (in dBc) measured when sinusoidal noise with ampitude VN and frequency fN (between 100 kHz and 1 MHz) is injected onto VDD and VDDO_x pins.
(7) DJSPUR (ps pk-pk) = [2 × 10(dBc/20) / (π × fOUT) × 1E6], where dBc is the PSNR or SPUR level (in dBc) and fOUT is the output frequency (in MHz).
(8) Actual loop bandwidth may be lower. The valid loop bandwidth range may be constrained by the DPLL TDC frequency used in a given configuration. 
(9) Parameter is specified for PLL outputs divided from either VCO domain.
(10) DPLL closed-loop jitter peaking of 0.1 dB or less is based on the DPLL bandwidth setting configured by the TICS Pro software tool.
(11) Minimum limit applies for the minimum setting of the differential input amplitude monitor (xREF_LVL_SEL = 0).
(12) Measured on the differential output waveform (OUTx_P - OUTx_N). Output with 2-pF load.
(13) To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns.  This is especially true for single-ended clocks.  Phase noise performance will begin to degrade as the clock input slew rate is reduced.  However, the device will function at slew rates down to the minimum listed.  When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. TI also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.
(14) Excluding output coupling spurs