Ultra-low jitter single channel network synchronizer clock with BAW


Product details


Function Clock network synchronizer Number of outputs 8 RMS jitter (fs) 50 Output frequency (Min) (MHz) 0.000001 Output frequency (Max) (MHz) 800 Input type LVCMOS, LVDS, LVPECL, XTAL Output type LVDS, CML, LVPECL, HCSL, LVCMOS Supply voltage (Min) (V) 3.135 Supply voltage (Max) (V) 3.465 Operating temperature range (C) -40 to 85 open-in-new Find other Clock jitter cleaners & synchronizers

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other Clock jitter cleaners & synchronizers


  • One Digital Phase-Locked Loop (DPLL) With:
    • Hitless Switching: ±50-ps Phase Transient
    • Programmable Loop Bandwidth With Fastlock
    • Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
  • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter Performance:
    • 50-fs RMS Jitter at 312.5 MHz (APLL1)
    • 125-fs RMS Jitter at 155.52 MHz (APLL2)
  • Two Reference Clock Inputs
    • Priority-Based Input Selection
    • Digital Holdover on Loss of Reference
  • Eight Clock Outputs with Programmable Drivers
    • Up to Six Different Output Frequencies
    • AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-V LVCMOS Output Formats
  • EEPROM / ROM for Custom Clocks on Power-Up
  • Flexible Configuration Options
    • 1 Hz (1 PPS) to 800 MHz on Input and Output
    • XO/TCXO/OCXO Input: 10 to 100 MHz
    • DCO Mode: < 0.001 ppb/Step for Precise Clock Steering (IEEE 1588 PTP Slave)
    • Advanced Clock Monitoring and Status
    • I2C or SPI Interface
  • PSNR: –83 dBc (50-mVpp Noise on 3.3-V Supply)
  • 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
  • Industrial Temperature Range: –40 °C to +85 °C
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The LMK05318B is high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The ultra-low jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links.

The device can generate output clocks with 50-fs RMS jitter using TI’s proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.

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Technical documentation

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Type Title Date
* Data sheet LMK05318B Ultra-Low Jitter Clock Generator datasheet (Rev. B) Jun. 21, 2021
User guide LMK05318B Register Programming Manual (Rev. A) Apr. 01, 2021
Certificate LMK05318BEVM EU Declaration of Conformity (DoC) Jun. 03, 2020
Application note ITU-T G.8262 compliance test results for the LMK05318 (Rev. A) Feb. 22, 2019
Application note Supported synchronization modes for TI network synchronizers (Rev. A) Feb. 22, 2019
Application note Understanding clocking needs for high-speed 56G PAM-4 serial links (Rev. A) Feb. 22, 2019
White paper TI BAW technology enables ultra-low jitter clocks for high-speed networks Feb. 17, 2019
Application note How to use the LMK05318 as a jitter cleaner Jan. 16, 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
To get started with this evaluation module:
Step 1: Buy the EVM
Step 2: Setup the default jumpers as shown in the user's guide
Step 3: Download TICS Pro and follow the EVM quick start instructions

This is an evaluation module (EVM) for the LMK05318B network synchronizer clock device.
The EVM can be used (...)
  • One Digital PLL (DPLL) with programmable bandwidths and two fractional analog PLLs (APLLs) for flexible clock generation
  • Two reference inputs to the DPLL supporting hitless switching & holdover
  • Eight output clocks with 50-fs RMS phase jitter (12 kHz to 20 MHz)
  • On-chip EEPROM for custom start-up clock (...)

Software development

SNAC072AK.ZIP (62249 KB)

Design tools & simulation

SNAM226.ZIP (137 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
  • Presents clear and intuitive block (...)

CAD/CAE symbols

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