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LMK05318B

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Ultra-low jitter single channel network synchronizer clock with BAW

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Data sheet

LMK05318B

ACTIVE
Data sheet Order now

Product details

Function Clock network synchronizer Number of outputs 8 RMS jitter (fs) 50 Output frequency (min) (MHz) 0.000001 Output frequency (max) (MHz) 800 Input type LVCMOS, LVDS, LVPECL, XTAL Output type CML, HCSL, LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Features I2C, Integrated EEPROM, Pin programmable, SPI Rating Catalog Operating temperature range (°C) -40 to 85 Number of input channels 2
Function Clock network synchronizer Number of outputs 8 RMS jitter (fs) 50 Output frequency (min) (MHz) 0.000001 Output frequency (max) (MHz) 800 Input type LVCMOS, LVDS, LVPECL, XTAL Output type CML, HCSL, LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Features I2C, Integrated EEPROM, Pin programmable, SPI Rating Catalog Operating temperature range (°C) -40 to 85 Number of input channels 2
VQFN (RGZ) 48 49 mm² 7 x 7
  • One Digital Phase-Locked Loop (DPLL) With:
    • Hitless Switching: ±50-ps Phase Transient
    • Programmable Loop Bandwidth With Fastlock
    • Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
  • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter Performance:
    • 50-fs RMS Jitter at 312.5 MHz (APLL1)
    • 125-fs RMS Jitter at 155.52 MHz (APLL2)
  • Two Reference Clock Inputs
    • Priority-Based Input Selection
    • Digital Holdover on Loss of Reference
  • Eight Clock Outputs with Programmable Drivers
    • Up to Six Different Output Frequencies
    • AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-V LVCMOS Output Formats
  • EEPROM / ROM for Custom Clocks on Power-Up
  • Flexible Configuration Options
    • 1 Hz (1 PPS) to 800 MHz on Input and Output
    • XO/TCXO/OCXO Input: 10 to 100 MHz
    • DCO Mode: < 0.001 ppb/Step for Precise Clock Steering (IEEE 1588 PTP Slave)
    • Advanced Clock Monitoring and Status
    • I2C or SPI Interface
  • PSNR: –83 dBc (50-mVpp Noise on 3.3-V Supply)
  • 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
  • Industrial Temperature Range: –40 °C to +85 °C
  • One Digital Phase-Locked Loop (DPLL) With:
    • Hitless Switching: ±50-ps Phase Transient
    • Programmable Loop Bandwidth With Fastlock
    • Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
  • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter Performance:
    • 50-fs RMS Jitter at 312.5 MHz (APLL1)
    • 125-fs RMS Jitter at 155.52 MHz (APLL2)
  • Two Reference Clock Inputs
    • Priority-Based Input Selection
    • Digital Holdover on Loss of Reference
  • Eight Clock Outputs with Programmable Drivers
    • Up to Six Different Output Frequencies
    • AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-V LVCMOS Output Formats
  • EEPROM / ROM for Custom Clocks on Power-Up
  • Flexible Configuration Options
    • 1 Hz (1 PPS) to 800 MHz on Input and Output
    • XO/TCXO/OCXO Input: 10 to 100 MHz
    • DCO Mode: < 0.001 ppb/Step for Precise Clock Steering (IEEE 1588 PTP Slave)
    • Advanced Clock Monitoring and Status
    • I2C or SPI Interface
  • PSNR: –83 dBc (50-mVpp Noise on 3.3-V Supply)
  • 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
  • Industrial Temperature Range: –40 °C to +85 °C

The LMK05318B is high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The ultra-low jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links.

The device can generate output clocks with 50-fs RMS jitter using TI’s proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.

The LMK05318B is high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The ultra-low jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links.

The device can generate output clocks with 50-fs RMS jitter using TI’s proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.
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Technical documentation

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Type Title Date
* Data sheet LMK05318B Ultra-Low Jitter Clock Generator datasheet (Rev. B) PDF | HTML 21 Jun 2021
User guide LMK05318B Register Programming Manual (Rev. A) 01 Apr 2021
Certificate LMK05318BEVM EU Declaration of Conformity (DoC) 03 Jun 2020
More literature ITU-T G.8262 compliance test results for the LMK05318 (Rev. A) 22 Feb 2019
More literature Supported synchronization modes for TI network synchronizers (Rev. A) 22 Feb 2019
More literature Understanding clocking needs for high-speed 56G PAM-4 serial links (Rev. A) 22 Feb 2019
More literature TI BAW technology enables ultra-low jitter clocks for high-speed networks 17 Feb 2019
More literature How to use the LMK05318 as a jitter cleaner 16 Jan 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK05318BEVM — Network synchronizer clock evaluation module

This is an evaluation module (EVM) for the LMK05318B network synchronizer clock device.
The EVM can be used as a flexible, synchronous clock source for rapid evaluation, compliance testing, and system prototyping. SMA ports provide access to the LMK05318B clock inputs and outputs for interfacing to (...)

User guide: PDF
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Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
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Simulation model

LMK05318 IBIS Model

SNAM226.ZIP (137 KB) - IBIS Model
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RGZ) 48 View options

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