SNAS829A October   2021  – January 2022 LMK1D2106 , LMK1D2108

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVDS Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 Input Termination

The LMK1D210x inputs can be interfaced with LVDS, LVPECL, HCSL, or LVCMOS drivers.

LVDS drivers can be connected to LMK1D210x inputs with DC and AC coupling as shown Figure 8-3 and Figure 8-4, respectively.

GUID-FEE9DD6B-5FE4-4A60-BCDD-F89EDA637ED6-low.gifFigure 8-3 LVDS Clock Driver Connected to LMK1D210x Input (DC-Coupled)
GUID-6E191598-EBCC-438D-B968-75DCB598E78B-low.gifFigure 8-4 LVDS Clock Driver Connected to LMK1D210x Input (AC-Coupled)

Figure 8-5 shows how to connect LVPECL inputs to the LMK1D210x. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6 VPP.

GUID-9766D08F-E466-44A4-85C4-E6B72566C0CC-low.gifFigure 8-5 LVPECL Clock Driver Connected to LMK1D210x Input

Figure 8-6 shows how to couple a LVCMOS clock input to the LMK1D210x directly.

Figure 8-6 1.8-V, 2.5-V, or 3.3-V LVCMOS Clock Driver Connected to LMK1D210x Input

For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩ resistors.