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LMK1D2106

ACTIVE

Dual bank 6-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer

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Data sheet

LMK1D2106

ACTIVE
Data sheet Order now

Product details

Function Clock buffer, Differential Additive RMS jitter (typ) (fs) 45 Output frequency (max) (MHz) 2000 Number of outputs 12 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features Dual 1:6 fanout, Output enable control, Universal inputs Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
Function Clock buffer, Differential Additive RMS jitter (typ) (fs) 45 Output frequency (max) (MHz) 2000 Number of outputs 12 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features Dual 1:6 fanout, Output enable control, Universal inputs Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
VQFN (RHA) 40 36 mm² 6 x 6
  • High-performance LVDS clock buffer family: up to 2 GHz
    • Dual 1:6 differential buffer
    • Dual 1:8 differential buffer
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
    • Very low phase noise floor: -164 dBc/Hz (typical)
  • Very low propagation delay: < 575 ps maximum
  • Output skew: 20 ps maximum
  • High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
  • Bank enable/disable using the EN pin
  • Fail-safe input operation
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packaged in

    • LMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)

    • LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)
  • High-performance LVDS clock buffer family: up to 2 GHz
    • Dual 1:6 differential buffer
    • Dual 1:8 differential buffer
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
    • Very low phase noise floor: -164 dBc/Hz (typical)
  • Very low propagation delay: < 575 ps maximum
  • Output skew: 20 ps maximum
  • High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
  • Bank enable/disable using the EN pin
  • Fail-safe input operation
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packaged in

    • LMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)

    • LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6).

Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6).

Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
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* Data sheet LMK1D210x Low Additive Jitter LVDS Buffer datasheet (Rev. A) PDF | HTML 28 Jan 2022

Design & development

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Evaluation board

LMK1D1212EVM — LMK1D1212 low jitter 2:12 LVDS fan-out buffer evaluation module

LMK1D1212 is a high-performance, low additive jitter LVDS clock buffer with two differential inputs and 12 LVDS outputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1D1212. This EVM can also be used to evaluate other 40 pin devices in the LMK1Dxxxx (...)
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LMK1DX IBIS Model (Rev. A)

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RHA) 40 View options
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