SNAS687C June   2016  – November 2017 LMK60A0-148351 , LMK60A0-148M , LMK60E0-156257 , LMK60E2-150M

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  LVPECL Output Characteristics
    7. 6.7  LVDS Output Characteristics
    8. 6.8  HCSL Output Characteristics
    9. 6.9  OE Input Characteristics
    10. 6.10 Frequency Tolerance Characteristics
    11. 6.11 Power-On/Reset Characteristics (VDD)
    12. 6.12 PSRR Characteristics
    13. 6.13 PLL Clock Output Jitter Characteristics
    14. 6.14 Additional Reliability and Qualification
    15. 6.15 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Ensuring Thermal Reliability
      2. 9.1.2 Best Practices for Signal Integrity
      3. 9.1.3 Recommended Solder Reflow Profile
  10. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • SIA|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Parameter Measurement Information

Device Output Configurations

LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M lvpecl_output_dc_configuration_snas687.gif Figure 4. LVPECL Output DC Configuration During Device Test
LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M lvds_output_dc_configuration_snas687.gif Figure 5. LVDS Output DC Configuration During Device Test
LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M hcsl_output_dc_configuration_snas687.gif Figure 6. HCSL Output DC Configuration During Device Test
LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M lvpecl_output_ac_configuration_snas687.gif Figure 7. LVPECL Output AC Configuration During Device Test
LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M lvds_output_ac_configuration_snas687.gif Figure 8. LVDS Output AC Configuration During Device Test
LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M hcsl_output_ac_configuration_snas687.gif Figure 9. HCSL Output AC Configuration During Device Test
LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M psrr_test_setup_snas687.gif Figure 10. PSRR Test Setup
LMK60E2-150M LMK60E0-156257 LMK60A0-148351 LMK60A0-148M differential_output_voltage_rise_fall_time_snas674.gif Figure 11. Differential Output Voltage and Rise/Fall Time