7.1.1 Theory of Operation

The schematic shown in the Functional Block Diagram gives a basic representation of the internal operation of the LMP860x and LMP860x-Q1.

The signal on the input pins is typically a small differential voltage developed across a current sensing shunt resistor. The input signal may also appear at a high common-mode voltage. The input signals are accessed through two input resistors that change the voltage into a current. The proprietary chopping level-shift current circuit pulls or pushes current through the input resistors to bring the common-mode voltage behind these resistors within the supply rails.

Subsequently, the signal is gained up by a factor of 10 and brought out on the A1 pin through a trimmed 100-kΩ resistor. In the application, additional gain adjustment or filtering components can be added between the A1 and A2 pins as explained in subsequent sections. The signal on the A2 pin is further amplified by a factor of 2 (LMP8601 and LMP8601-Q1), 5 (LMP8602, LMP8602-Q1), or 10 (LMP8603, LMP8603-Q1), and brought out on the OUT pin.

7.3.1 Offset Input Pin

The OFFSET pin allows the output signal to be level-shifted to enable bidirectional current sensing. The output signal is bidirectional and mid-rail referenced when the offset pin is connected to the positive supply rail. With the offset pin connected to ground, the output signal is unidirectional and ground-referenced.

The signal on the A1 and OUT pins is ground-referenced when the offset pin is connected to ground. This means that the output signal can only represent positive values of the current through the shunt resistor, so only currents flowing in one direction can be measured.

When the offset pin is tied to the positive supply rail, the signal on the A1 and OUT pins is referenced to a mid-rail voltage which allows bidirectional current sensing. The operation of the amplifier will be fully bidirectional and symmetrical around 0 V differential at the input pins. The signal at the output will follow this voltage difference multiplied by the gain and at an offset voltage at the output of half V_S.

When the offset pin is connected to an external voltage source, the output signal will be level shifted to that voltage divided by two. In principle, the output signal can be shifted to any voltage between 0 and V_S / 2 by applying twice that voltage to the OFFSET pin.

Examples:

• LMP8601, LMP8601-Q1: A 5-V supply, a gain of 20x, OFFSET pin tied to V_S, and a differential input signal of 10 mV results in 2.7 V at the output pin. Similarly, –10 mV at the input results in 2.3 V at the output pin.
• LMP8602, LMP8602-Q1: A 5-V supply, a gain of 50x, and a differential input signal of 10 mV results in 3.0 V at the output pin. Similarly, –10 mV at the input results in 2.0 V at the output pin.
• LMP8603, LMP8603-Q1: A 5-V supply, a gain of 100x, and a differential input signal of 10 mV results in 3.5 V at the output pin. Similarly, –10 mV at the input results in 1.5 V at the output pin.

7.3.2 Additional Second-Order Low-Pass Filter

The LMP86x1 and LMP86x1-Q1 have a third-order Butterworth lowpass characteristic with a typical bandwidth of 60 kHz integrated in the preamplifier stage. The bandwidth of the output buffer can be reduced by adding a capacitor on the A1 pin to create a first-order low-pass filter with a time constant determined by the 100-kΩ internal resistor and the external filter capacitor.

It is also possible to create an additional second-order, Sallen-Key, low-pass filter by adding external components R₂, C₁ and C₂. Together with the internal 100-kΩ resistor R₁ as illustrated in Figure 53, this circuit creates a second-order, low-pass filter characteristic.

NOTE: K1 = 10; K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1.

Figure 53. Second-Order Low-Pass Filter

When the corner frequency of the additional filter is much lower than 60 kHz, the transfer function of the described amplifier can be written as:

Equation 1.

where

• K₁ equals the gain of the preamplifier and K₂ that of the buffer amplifier.

Equation 1 can be written in the normalized frequency response for a second-order lowpass filter:

Equation 2.

The cutoff frequency ω_o in rad/sec (divide by 2π to get the cut-off frequency in Hz) is given by:

Equation 3.

and the quality factor of the filter is given by:

Equation 4.

With K₂ = 2x, Equation 4 transforms results in:

Equation 5.

For any filter gain K > 1x, the design procedure can be very simple if the two capacitors are chosen to in a certain ratio.

Equation 6.

Inserting this in Equation 4 for Q results in:

Equation 7.

Which results in:

Equation 8.

In this case, given the predetermined value of R1 = 100 kΩ (the internal resistor), the quality factor is set solely by the value of the resistor R₂.

R₂ can be calculated based on the desired value of Q as the first step of the design procedure with the following equation:

Equation 9.

For the gain of 2 for the LMP8601 and LMP8601-Q1, the result is:

Equation 10.

For the gain of 5 for the LMP8602 and LMP8602-Q1, the result is:

Equation 11.

For the gain of 10 for the LMP8603 and LMP8603-Q1, the result is:

Equation 12.

For instance, the value of Q can be set to 0.5√2 to create a Butterworth response, to 1/√3 to create a Bessel response, or a 0.5 to create a critically damped response. After the value of R₂ has been found, the second and last step of the design procedure is to calculate the required value of C to give the desired low-pass cut-off frequency using:

Equation 13.

For the gain = 2, the result is:

Equation 14.

The gain = 5 results in:

Equation 15.

The gain = 10 gives:

Equation 16.

For C₂ the value is calculated with:

Equation 17.

For a gain = 2:

Or for a gain = 5:

Equation 19.

And for a gain = 10:

Equation 20.

Note that the frequency response achieved using this procedure is only accurate if the cut-off frequency of the second-order filter is much smaller than the intrinsic 60-kHz, low-pass filter. In other words, choose the frequency response of the LMP860x or LMP860x-Q1 circuit so that the internal poles do not affect the external second-order filter.

7.4.1 Gain Adjustment

The gain of the LMP860x and LMP860x-Q1 is fixed; however, the overall gain may be adjusted as the signal path between the two internal amplifiers is available on the A1 and A2 pins.

7.4.1.1 Reducing Gain

Figure 54 shows the configuration that can be used to reduce the gain of the LMP8601 and LMP8601-Q1.

NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1.

Figure 54. Reduce Gain

R_r creates a resistive divider together with the internal 100-kΩ resistor such that the reduced gain G_r becomes:

Equation 21.

For the LMP8602 and LMP8602-Q1:

Equation 22.

And for the LMP8603 and LMP8603-Q1:

Equation 23.

Given a desired value of the reduced gain G_r, using this equation, the LMP8601 and LMP8601-Q1 required value for the R_r is calculated with:

Equation 24.

For the LMP8602 and LMP8602-Q1:

Equation 25.

And for the LMP8603 and LMP8603-Q1:

Equation 26.

7.4.1.2 Increasing Gain

Figure 55 shows the configuration that can be used to increase the gain of the LMP8601 and LMP8601-Q1.

NOTE: K2 = 2 for LMP8601, LMP8601-Q1; 5 for LMP8602, LMP8602-Q1; or 10 for LMP8603, LMP8603-Q1.

Figure 55. Increase Gain

R_i creates positive feedback from the output pin to the input of the buffer amplifier. The positive feedback increases the gain. The increased gain G_i for the LMP8601 and LMP8601-Q1 becomes:

Equation 27.

For the LMP8602 and LMP8602-Q1:

Equation 28.

And for the LMP8603 and LMP8603-Q1:

Equation 29.

From this equation, for a desired value of the gain, the LMP8601 and LMP8601-Q1 required value of R_i is calculated with:

Equation 30.

For the LMP8602 and LMP8602-Q1:

Equation 31.

And for the LMP8603 with:

Equation 32.

Note that from the equation for the gain G_i, for large gains, R_i approaches 100 kΩ. In this case, the denominator in the equation becomes close to zero. In practice, for large gains, the denominator is determined by tolerances in the value of the external resistor R_i and the internal 100-kΩ resistor. In this case, the gain becomes very inaccurate. If the denominator becomes equal to zero, the system becomes unstable. TI recommends to limit the application of this technique to gain values of 50 or smaller.

7.4.2 Driving Switched Capacitive Loads

Some ADCs load their signal source with a sample and hold capacitor. The capacitor may be discharged prior to being connected to the signal source. If the LMP860x and LMP860x-Q1 are driving such ADCs, the sudden current that should be delivered when the sampling occurs may disturb the output signal. This effect was simulated with the circuit shown in Figure 56 where the output is to a capacitor that is driven by a rail-to-rail square wave.

Figure 56. Driving Switched Capacitive Load

This circuit simulates the switched connection of a discharged capacitor to the LMP860x and LMP860x-Q1 output. The resulting V_OUT disturbance signals are shown in Figure 57 and Figure 58.

Figure 57. Capacitive Load Response at 3.3 V

Figure 58. Capacitive Load Response at 5.0 V

These figures can be used to estimate the disturbance that will be caused when driving a switched capacitive load. To minimize the error signal introduced by the sampling that occurs on the ADC input, place an additional RC filter between the LMP860x or LMP860x-Q1 and the ADC, as illustrated in Figure 59.

Figure 59. Reduce Error When Driving ADCs

The external capacitor absorbs the charge that flows when the ADC sampling capacitor is connected. The external capacitor should be much larger than the sample-and-hold capacitor at the input of the ADC, and the RC time constant of the external filter should be such that the speed of the system is not affected.