SNAS634B March   2014  – January 2016 LMP92066

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Output Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Features Description
      1. 8.3.1 Temperature Sensor
      2. 8.3.2 Look-Up-Table (LUT) and Arithmetic-Logic Unit (ALU)
        1. 8.3.2.1 LUT and ALU Organization
        2. 8.3.2.2 LUT Coefficient to Register Mapping
        3. 8.3.2.3 The LUT Input and Output Ranges
      3. 8.3.3 Analog Signal Path
        1. 8.3.3.1 DAC
        2. 8.3.3.2 Buffer Amplifier
        3. 8.3.3.3 Output On and Off Control
      4. 8.3.4 Memory
        1. 8.3.4.1 READ and WRITE Access
        2. 8.3.4.2 Access Control
        3. 8.3.4.3 LUT, NOTEPAD Storage, and EEPROM
      5. 8.3.5 I2C Interface
        1. 8.3.5.1 Supported Data Transfer Formats
        2. 8.3.5.2 Slave Address Selection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Default Operating Mode
      2. 8.4.2 Temperature Sensor Override
      3. 8.4.3 ALU Bypass
      4. 8.4.4 DAC Input Override
      5. 8.4.5 LDMOS and GaN Drives
    5. 8.5 Programming
      1. 8.5.1  Temperature Sensor Output Data Access Registers
      2. 8.5.2  DAC Input Data Registers
      3. 8.5.3  Temperature Sensor Status Register
      4. 8.5.4  Override Control Register
      5. 8.5.5  Override Data Registers
      6. 8.5.6  EEPROM Control Register
      7. 8.5.7  Software RESET Register
      8. 8.5.8  Access Control Register
      9. 8.5.9  Block I2C Access Control Register
      10. 8.5.10 I2C Address LOCK Register
      11. 8.5.11 Output Drive Supply Status Register
      12. 8.5.12 Device Version Register
      13. 8.5.13 EEPROM Burn Counter
      14. 8.5.14 LUT Coefficient Registers
      15. 8.5.15 LUT Control Registers
      16. 8.5.16 Notepad Registers
    6. 8.6 Register Map
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Temperature Compensated Bias Generator for LDMOS Power Amplifer (PA)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Requirements
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Temperature Compensated Bias Generator for GaN Power Amplifer (PA)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Output Drive Switching
    4. 9.4 Initialization Setup
      1. 9.4.1 Factory Default
      2. 9.4.2 At Power Up
  10. 10Power Supply Recommendations
    1. 10.1 VDD Supply Sourcing
    2. 10.2 IVDD During EEPROM BURN
    3. 10.3 IVDD During EEPROM TRANSFER
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LMP92066 was designed for ease of use. The device requires minimum external components to realize its full functionality. In the typical application the bulk of the design effort is spent on characterization of the target transfer function, and then developing a set of coefficients that the LMP92066 to accurately reproduce the target function.

NOTE

The LMP92066 can approximate temperature dependent functions, VDAC0,1(T), only if the following requirements are met:

  1. Each VDAC0,1(T) must be unipolar. The range of the function must be either wholly positive, or wholly negative. This is dictated by the structure of the Buffer Amplifier that drives the FETDRVx. See the Buffer Amplifier section.
  2. Both functions VDAC0,1(T) must be of the same polarity. See the Buffer Amplifier section.
  3. Each VDAC0,1(T) must be monotonic. This is dictated by the structure of the LUTs. See the LUT and ALU Organization section.
  4. The maximum slope of each VDAC0,1(T) is no greater than 4.88 mV/°C. This also limits the maximum range, the minimum to maximum span, for the VDAC0,1(T) to 761 mV. This is due to the fact that the LUT stores the slope of the VDAC0,1(T) as 4-bit values. See the The LUT Input and Output Ranges section.

9.2 Typical Applications

9.2.1 Temperature Compensated Bias Generator for LDMOS Power Amplifer (PA)

The typical application for the LMP92066 is the biasing of the power amplifiers in an RF system. What is required in such applications is for the PA drain current to remain constant over a wide range of operating temperatures. The LMP92066 senses the PA temperature and adjust the bias potential at the gate of the PA in accordance with the known VGS(T), at ID = constant, characteristic of the PA.

The typical application circuit for LDMOS applications is shown in Figure 39. A thermal path has to be provided between the LMP92066 and the PA. This is typically accomplished through the close proximity of the 2 devices, and the common metal layer. See also the Layout Example.

LMP92066 typ_app_LDMOS_snas634.gif Figure 39. Temperature-Compensated Bias Generator
for LDMOS Power Amplifier (PA)

9.2.1.1 Design Requirements

The thermal characteristic of a hypothetical LDMOS PA is plotted in Figure 40. This characteristic was obtained from the temperature sweep of the LDMOS gate-source voltage, VGS, while keeping the drain current, ID = 750 mA. The goal is to have the LMP92066 produce that same VGS vs T characteristic which, when applied to the gate of the PA device ensures constant ID throughout the operating temperature range.

In the following sections the curve VGS vs T are referred to as the Target Function, VDAC (T).

LMP92066 C023_snas634.png Figure 40. Target Function to be Reproduced by the LMP92066:
VGS vs T Characteristic of an LDMOS PA

The target function is approximated by the following polynomial (T unit is °C):

Equation 7. LMP92066 eq11_snas634.gif

In the Detailed Design Requirements section the above expression is used to obtain the LUT coefficient values.

9.2.1.2 Detailed Design Requirements

Figure 41 outlines the LUT design procedure. The procedure is for one channel only – repeat for the second available channel, as needed. In principle, the procedure follows the signal path backwards from the output, which is ideally the target function VDAC(T), back to the LUT coefficients, and each block’s processing has to be “reversed”. Additional comments for each design step are listed below Figure 41.

LMP92066 LUTdesign_procedure.gif Figure 41. Flowchart of the Generalized LUT Design Procedure
  1. Before attempting to calculate the LUT coefficients for the given target function VDAC(T), verify the requirements listed in the Application Information section are met.
  2. Test if the function is wholly positive, or negative. If necessary “undo” the action of the Buffer Amplifier. (See the Buffer Amplifier section.) From now on consider the pre-buffer signal pBUFF(T). The design variable set in this step is the state of the VDDB and VSSB supplies. VDAC(T) is a strictly positive valued function, therefore:

    3. Equation 8. LMP92066 eq06_snas634.gif
  3. Check the slope of the pBUF(T). Record the sign of the slope, and from here on consider a positive slope function cG(T). The design variable set in this step is the POL bit. pBUFF(T) is a monotonically increasing function, therefore:

    4. Equation 9. LMP92066 eq07_snas634.gif
  4. Discretize the continuous cG(T) along its temperature domain, thus creating the sequence G(k). Maintain the full precision of the G(k) values. Note the full precision cG(T) at T = 24°C — this is the full precision BASE value, fpBASE, still in voltage domain.

    5. LMP92066 eq02_snas634.gif
  5. Apply difference operation to the G(k) sequence, and obtain new sequence fpDEL(k). These are now the full precision increments of the target function with each 4°C interval.

    6. LMP92066 eq03_snas634.gif
  6. Convert the full precision voltages of fpDEL(k) and fpBASE to a numeric, quantized domain. This reverses the DAC action.

    7. LMP92066 eq04_snas634.gif
  7. Usually BYP bit is reset, BYP=0. However, in cases where it is desirable to bypass the LUT and ALU, and have the DACx output produce voltage equivalent of the BASE value, set BYP = 1.
  8. Repeat steps 1 to 6 to obtain POL, BYP, BASE, DELx values for the second channel.
  9. Now have BYP, POL, BASE, and DEL(0..38) values ready to be programmed into the LUT.

NOTE

The device has to be in the L2 Access Level before commencing the WRITE access of BYP, POL, BASE, DELx values. The register WRITE operation immediately affects the operation of the device. However, operating memory is volatile, and BURN operation is required to commit the LUT coefficients to non-volatile memory, EEPROM.

9.2.1.3 Application Curves

The output of the LMP92066 due to the coefficients calculated in the above procedure is shown in Figure 42.

Figure 43 shows the absolute difference between the target function and the measured response of the LMP92066.

LMP92066 C024_snas634.png Figure 42. Measured Response of the LMP92066
Resulting from the LUT Coefficients
(see Detailed Design Requirements)
LMP92066 C025_snas634.png Figure 43. Difference Between the Target Response
shown in Figure 40 and
Measured Response in Figure 42

9.2.2 Temperature Compensated Bias Generator for GaN Power Amplifer (PA)

The typical application for the LMP92066 is the biasing of the power amplifiers in an RF system. What is required in such applications is for the PA drain current to stay constant over a wide range of operating temperatures. The LMP92066 senses the PA temperature and adjust the bias potential at the gate of PA in accordance with the known VGS(T), at ID = constant, characteristic of the PA.

LMP92066 typ_app_GaN_snas634.gif Figure 44. Temperature-Compensated Bias Generator
for GaN Power Amplifier (PA)

9.2.2.1 Design Requirements

The thermal characteristic of a hypothetical GaN PA is plotted in Figure 45. This characteristic was obtained from the temperature sweep of the GaN gate-source voltage, VGS, while keeping the drain current, ID = 750 mA. The goal is to have the LMP92066 produce that same VGS vs T characteristic which, when applied to the gate of the PA device ensures constant ID throughout the operating temperature range.

In the following sections the curve VGS vs T is referred to as the Target Function, VDAC (T).

LMP92066 C026_snas634.png Figure 45. The Target Function to be Reproduced by the LMP92066:
VGS vs T Characteristic of an GaN PA

The target function is approximated by the following polynomial (T unit is °C):

9.2.2.2 Detailed Design Procedure

Figure 46 outlines the LUT design procedure. The procedure is for one channel only – repeat for the second available channel, as needed.

In principle, the procedure follows the signal path backwards from the output, which is ideally the target function VDAC(T), back to the LUT coefficients, reversing the processing of each block. Additional comments for each design step are listed below Figure 46.

LMP92066 LUTdesign_procedure.gif Figure 46. Flowchart of the Generalized LUT Design Procedure
  1. Before attempting to calculate the LUT coefficients for the given target function VDAC(T), verify the requirements listed in the Application Information section are met.
  2. Test if the function is wholly positive, or negative. If necessary “undo” the action of the Buffer Amplifier. (See the Buffer Amplifier section.) From now on consider the pre-buffer signal pBUFF(T). The design variable set in this step is the state of the VDDB, VSSB supplies. VDAC(T) is a strictly positive valued function, therefore:

    3. Equation 10. LMP92066 eq14_snas634.gif
  3. Check the slope of the pBUF(T). Record the sign of the slope, and from here on consider a positive slope function cG(T). The design variable set in this step is the POL bit. pBUFF(T) is a monotonically increasing function, therefore:

    4. Equation 11. LMP92066 eq07_snas634.gif
  4. Discretize the continuous cG(T) along its temperature domain, thus creating the sequence G(k). Maintain the full precision of the G(k) values. Note the full precision cG(T) at T = 24°C — this is the full precision BASE value, fpBASE, still in voltage domain.

    5. Equation 12. LMP92066 eq08_snas634.gif
  5. Apply difference operation to the G(k) sequence, and obtain new sequence fpDEL(k). These are now the full precision increments of the target function with each 4°C interval.

    6. LMP92066 eq09_snas634.gif
  6. Convert the full precision voltages of fpDEL(k) and fpBASE to a numeric, quantized domain. This reverses the DAC action.

    7. LMP92066 eq10_snas634.gif
  7. Usually BYP bit is reset, BYP=0. However, in cases where it is desirable to bypass the LUT and ALU, and have the DACx output produce voltage equivalent of the BASE value, set BYP = 1.
  8. Repeat steps 1 to 6 to obtain POL, BYP, BASE, DELx values for the second channel.
  9. Now have BYP, POL, BASE, and DEL(0..38) values ready to be programmed into the LUT.

NOTE

The device has to be in the L2 Access Level before commencing the WRITE access of BYP, POL, BASE, DELx values. The register WRITE operation immediately affects the operation of the device. However, operating memory is volatile, and BURN operation is required to commit the LUT coefficients to non-volatile memory, EEPROM.

9.2.2.3 Application Curves

The output of the LMP92066 due to the coefficients calculated in the above procedure is shown in Figure 47.

Figure 48 shows the absolute difference between the target function and the measured response of the LMP92066.

LMP92066 C027_snas634.png Figure 47. Measured Response of the LMP92066 Resulting from the LUT Coefficients
(see Detailed Design Procedure)
LMP92066 C028_snas634.png Figure 48. Difference Between the Target Response
shown in Figure 45 and
Measured Response in Figure 47

9.3 Do's and Don'ts

9.3.1 Output Drive Switching

Some applications may require that the FETDRVx output reaches the level set by the DACx as fast as possible after the assertion of DRVENx.

There are parameters which determine the delay between the assertion of DRVENx, and the FETDRVx output achieving its final level as set by the DACx:

  • The delay between the DRVENx input the output switch.
  • The charge up time of the FETDRVx node once the output switch is closed.

The delay of the switch response to the DRVENx input, tON, is specified in the Electrical Characteristics table.

The charge up time of the FETDRVx node is dependent on the selection of the external components. Rapid rise time of the FETDRVx output, is made possible through the use of the external capacitor C1. C1 is always charged to the potential generated by the DACx, and used to provide instantaneous charge to the load present at the FETDRVx when the output switch closes – the switch between DACx and FETDRVx pin.

C1 is chosen to be several orders of magnitude larger than the total capacitance present at the FETDRVx pin, CEXT. In the typical application C1 is 10 µF, and CEXT is limited to 10 nF. See Figure 49. When the output switch closes, a current flows from the C1, acting as a reservoir, to CEXT. This charge-up current is limited only by the resistance of the output switch RDRV, resulting in very rapid slewing at the FETDRVx pin. RDRV is specified in the Electrical Characteristics table.

For example, given the following parameters.

  • tON = 50 ns
  • RDRV = 5 Ω
  • CEXT = 10 nF

The total delay time between activation of DRVENx and FETDRVx achieving 95% of its final value is:

Equation 13. TDELAY = tON+ 5τ = tON + 5RDRVCEXT = 300 ns

NOTE

The charge current flowing into the CEXT at the instant the output switch closes is relatively large and of very short duration, which makes the parasitic inductance in the charge path significant. This parasitic inductance is due to the bond wire and package pin between the device die and the CEXT, and is shown as LP in Figure 49. In some applications it may be beneficial to insert a small resistance in the charge path, see REXT in Figure 49, to dampen the resonance of the LP and CEXT. Choice of REXT is highly application dependent, but 5 Ω is a good initial selection.

LMP92066 charge_current.gif Figure 49. Flow of Charge Current

9.4 Initialization Setup

9.4.1 Factory Default

At the factory the EEPROM is initialized such that all LUT increment values (Δ) are set to 0, BASE value is set to 0x00, and BYP and POL bits are set to 0. This results in the device producing constant output of 0V at DACx pins upon power up, regardless of the temperature or mode or state at the DRVENx inputs.

9.4.2 At Power Up

The device is capable of autonomous operation upon power up, without intervention form the system controller. When the power is applied and reaches the minimum level (approximately 4.1 V) the temperature sensor begins operating, and the internal sequencer begins the transfer of LUT values from the EEPROM to the operating memory. Once the transfer is complete, and the Temperature Sensor has completed the first conversion, the ALU computes the DACs input values, and the DACs start producing output voltages representative of the transfer functions implemented in the LUTs.

The control signal applied to the DRVENx input determines whether the DAC output voltage is present at the FETDRVx output, or that output is driven to VSSB potential.

Figure 50 shows the typical power-up transient behavior at the DACx outputs. While VDD voltage is ramping up from 0 to 5 V the DACx outputs initially follow the VDD. This is due to the fact that initially the device is in the undefined state. When VDD reaches 4.1 V the internal reset occurs and clears the internal data path, resulting in VDACx = 0 V. The Temperature Sensor begins operation at the moment of reset, and 25 ms later produces its first temperature measurement. This, in turn, causes the ALU to update DAC input data, resulting in new VDACx output.

LMP92066 C020_snas634.gif
VDD = 2V/div VDAC1 = 1V/div VDAC0 = 1V/div
Figure 50. Power-Up Transient Behavior

See also the Default Operating Mode section.