SNAS633A March   2014  – September  2014 LMP93601

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Thermopile Array System Diagram
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Thermal Information
    4. 7.4 Electrical Characteristics
    5. 7.5 Timing Requirements
    6. 7.6 Noise Performance
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Data Format
      2. 8.3.2  Transfer Function
      3. 8.3.3  Input Routing Mux
      4. 8.3.4  Programmable Gain Amplifier
      5. 8.3.5  PGA Bypass Mode
      6. 8.3.6  Over-Range Detection
      7. 8.3.7  Analog-To-Digital Converter (ADC)
      8. 8.3.8  Programmable Digital Filters
      9. 8.3.9  Common Mode Voltage Generator
      10. 8.3.10 Low Drop-Out Regulator (LDO)
      11. 8.3.11 External Clock
      12. 8.3.12 Operating Modes
      13. 8.3.13 Data Ready Function (DRDYB)
      14. 8.3.14 Synchronous Serial Peripheral Interface (SPI)
      15. 8.3.15 Power Management Mode; Standby, Conversion and Shutdown
      16. 8.3.16 Power-On Sequence and Reset (POR) Function
      17. 8.3.17 Brown-Out Detection Function
      18. 8.3.18 Reset Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Single-Shot Mode
      2. 8.4.2 Continuous Mode
    5. 8.5 Programming
      1. 8.5.1 Window to Capture Data and Status
      2. 8.5.2 Single Byte Access
    6. 8.6 Register Maps
    7. 8.7 Multi Byte Access (Auto Increment) Mode
    8. 8.8 Multi-Channel Data Read
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

LMP93601
24 Pin
Top View
package_drawing01_snas633.gif

Pin Functions

PIN(2) TYPE(I/O)(1) DESCRIPTION
NAME NUMBER
VCM 1 Analog in/output Sensor common mode bias voltage
INP1 2 Analog input Input signal positive pin
INN1 3 Analog input Input signal negative pin
INP2 4 Analog input Input signal positive pin
INN2 5 Analog input Input signal negative pin
INP3 6 Analog input Input signal positive pin
INN3 7 Analog input Input signal negative pin
AGND 8 Analog ground
PWDNB 9 Digital input Enable, active low
RSTB 10 Digital input Master reset, active low
SYNC 11 Digital input Sync, active high
XCLK 12 Digital input External clock source
DRDYB 13 Digital output Data ready signal, active low, push-pull
SDI 14 Digital input Serial data input
CSB 15 Digital input Chip select, active low
IOGND 16 Digital IO ground
SCLK 17 Digital input Serial interface clock
SDO 18 Digital output Serial data output; push-pull
IOVDD 19 Digital IO supply rail
DGND 20 Digital ground
AGND 21 Analog ground
XCAP2 22 Digital LDO External Cap2
XCAP1 23 Analog External Cap1
AVDD 24 Analog Analog supply rail
(1) There is no pull-up/-down for any digital I/O
(2) For best performance, it is recommended that the DAP is connected to AGND (refer to Mechanical, Packaging and Orderable Information ). All three “GND” connections (AGND, DGND and IOGND) must be connected to system ground and cannot be left floating.